[Cryptech Tech] FPGAs for Dummies

[Joachim Strömbergson]

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Aloha!

Warren Kumari wrote:
>> I can only very kinda sorta understand a single threaded program. 
>> Throw in some sort of parallelism (like a thread or two) and I
>> start going cross-eyed. My mind simply shuts down when I need to
>> imagine "do this thing every time there is a clock cycle, don't
>> worry, the data will be there."

Yes, it is a challenge. Drawing the design on paper really helps. And
for datapaths, drawing clock lines makes it much easier to see what
happens when. Also, Verilog (and VHDL) is much more low level - you
really describe everything.

The design style I use is to place all registers in one process that
means that the updates in that process happens in parallel. But in all
other processes (which only contains logic), the code chunks is
sequential more or less like in a programming language. It really helps
for the understanding (imho). Oh, and all proceeses "runs" in parallel
and one needs to figure out how they interact, solve sharing between
them etc.

Take a look at the SipHash core for example and see if it makes sense:

https://github.com/secworks/siphash/blob/master/src/rtl/siphash_core.v

There is a bunch of declarations for registers, wires etc. Then you have
the register updates - this is where the registers becomes the
registers. This is followed by the real functional logic. It is
basically separate blocks of logic connected to a MUX that selects what
block gets to update the state registers.

The SipHash needs a counter and the counter logic is placed in a
separate process. Finally at the bottom of the file there is the logic
that implements the control finite state machine that decides what needs
to be done and when.

Does it make sense and is understandable?

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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