[Cryptech Tech] Some measurement results for FPGA with avalanche entropy source

[Joachim Strömbergson]

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Aloha!

Bernd Paysan wrote:
> The internal ROs won't pass dieharder without additional stuff, due
> to the bias.

That isn't the plan either. We will probably have entropy access ports
even in the first iteration. But I assume Randy meant being able to run
Dieharder on the output from the csprng. Just to be able to show that we
can deliver a working TRNG.


> I've been thinking about mixing them all together through one LSR, 
> which would work like this, with ro being 32 ring oscillator outputs
> (flip- flops, sampled each cycle):
> 
> reg [31:0] mix;
> 
> always @(posedge clk) mix <= ro ^ { mix[30:0], ~mix[31] };
> 
> and sampling mix every multiple of 64 cycles (better accumulate for
> 128 cycles).
> 
> This function eliminates biases (after 64 rounds, we have 32 inverted
> and 32 non-inverted samples xored together in each bit), and still is
> simple enough that all real failures of the ring oscillators (like
> aligned oscillation or insufficient jitter) will show up.

Cool. I'll try to implement and test that.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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