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[Joachim Strömbergson]

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Aloha!

Sorry for a late reply on this. Thanks to FredrikT for reminding me.

Bernd Paysan wrote:
> I've just audited the code I originally contributed, and I have a
> serious question, regarding how much fluff went into that code (it's
> a complete rewrite, and even leaving away the copyrigth message and
> the comments, it's about a three-fold expansion):

The top level as well as _core code in core/rosc_entropy is a rewrite
since we want to different things, esp adding observation mechanism, but
also capture the events in a different way as suggested by Fischer.

The really cool, adder based oscillator functionality you came up with
is in rosv.v. You should be mentioned there and I will update the
authorship accordingly.

The code you provided is more preserved in the fpga_entropy and
bp_entropy cores under test/.

Regarding coding style and methods of implementation we clearly have
widely different views and experiences.

I'm basing my methods a lot on what I see are best practices, for
example from Cisco, Ericsson, but also from established experts such as
Sutherland and Cummings.

But there are also conflicting best practices. And if one starts to
target not only design guidelines from different FPGA vendors, but also
FPGA as well as possible ASIC designs with big tool chains the design
style used will become fairly conservative in language features and
stating hard absolutes in terms of what is the best way doesn't really
work. It is always a compromise.

- From my experience doing code auditing as well as working on big
designs, the claim that tersness is always better is not something I
agree with. If it was, IOCCC entries would be considered the pinnacle of
maintainable code.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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