[Cryptech Tech] EIM: mostly working
Paul Selkirk
paul at psgd.org
Thu Nov 6 21:55:53 UTC 2014
On 11/06/2014 03:27 AM, Joachim Strömbergson wrote:
> But do you get timing closure for these cores @133 MHz. I would have
> excected them to not be able to be clocked that high in the Spartan-6.
> What does the timing report says?
> (1) Ensure that all important timings are met. If not, signals will not
> have the correct, expected values. Can you extract the final timimg report?
I've attached build logs for both the 133MHz and 25MHz clocks. As
expected, there are timing differences.
Even clocking the coretest circuit at 25MHz, there are still reported
timing errors around the EIM code. Bunnie says:
///// It's tricky to change code that relates to
///// the details of talking to the i.MX6 EIM -- it's difficult to
///// close timing, so you'll need to understand a bit about FPGA timing
///// closure to make chages to that section
And I don't understand FPGA timing closure.
> (2) Ensure that the 16-32 bit and big endian-little endian-converion
> works as expected. How about adding a 32-bit register, write to it from
> EIM and the extract it via I2C. Since you have I2C access working you
> should be able to see if the conversion works as expected. That is we
> end up with the expected values in the FPGA.
>
> (3) Properly debug the EIM interface and the SW interface including
> setup with something simple. Possible a single hash core or something
> even simpler. An adder, multiplier etc with extra ports for debugging.
> Then we add one of the hash cores and then move towards the complete
> shebang.
Given that all 3 of the hash cores produce correct digests for single
and double block tests most of the time, I'm pretty confident in both of
these things. But I think we're riding the edge of our timing
tolerances, and it's biting us most often in the 1000-block test (while
the other tests hash 18 blocks in total).
paul
-------------- next part --------------
tin-man:~/coretest/core/novena_eim/build$ time make
echo "run" > novena_eim.scr
echo "-p xc6slx45csg324-3" >> novena_eim.scr
echo "-top novena_fpga" >> novena_eim.scr
echo "-ifn novena_eim.prj" >> novena_eim.scr
echo "-ofn novena_eim.ngc" >> novena_eim.scr
cat ./xilinx.opt >> novena_eim.scr
for src in ../../sha1/src/rtl/sha1.v ../../sha1/src/rtl/sha1_core.v ../../sha1/src/rtl/sha1_w_mem.v ../../sha256/src/rtl/sha256.v ../../sha256/src/rtl/sha256_core.v ../../sha256/src/rtl/sha256_k_constants.v ../../sha256/src/rtl/sha256_w_mem.v ../../sha512/src/rtl/sha512.v ../../sha512/src/rtl/sha512_core.v ../../sha512/src/rtl/sha512_h_constants.v ../../sha512/src/rtl/sha512_k_constants.v ../../sha512/src/rtl/sha512_w_mem.v ../src/rtl/common/sync_reset.v ../src/rtl/coretest_hashes.v ../src/rtl/ip/bclk_dll/bclk_dll.v ../src/rtl/ip/clk_dll/clk_dll.v ../src/rtl/ip/dcm_delay/dcm_delay.v ../src/rtl/novena_fpga.v ; do echo "verilog work $src" >> novena_eim.tmpprj; done
sort -u novena_eim.tmpprj > novena_eim.prj
rm -f novena_eim.tmpprj
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; xst -ifn novena_eim.scr
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - xst P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "novena_eim.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Target Device : xc6slx45csg324-3
Output File Name : "novena_eim.ngc"
Output Format : NGC
---- Source Options
Top Module Name : novena_fpga
Safe Implementation : No
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
ROM Style : Auto
Shift Register Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Keep Hierarchy : no
Netlist Hierarchy : as_optimized
RTL Output : no
Global Optimization : AllClockNets
Read Cores : yes
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_core.v" into library work
Parsing module <sha1_core>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha1/src/rtl/sha1.v" into library work
Parsing module <sha1>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_w_mem.v" into library work
Parsing module <sha1_w_mem>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_core.v" into library work
Parsing module <sha256_core>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_k_constants.v" into library work
Parsing module <sha256_k_constants>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256.v" into library work
Parsing module <sha256>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_w_mem.v" into library work
Parsing module <sha256_w_mem>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_core.v" into library work
Parsing module <sha512_core>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_h_constants.v" into library work
Parsing module <sha512_h_constants>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_k_constants.v" into library work
Parsing module <sha512_k_constants>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512.v" into library work
Parsing module <sha512>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_w_mem.v" into library work
Parsing module <sha512_w_mem>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/common/sync_reset.v" into library work
Parsing module <sync_reset>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" into library work
Parsing module <coretest_hashes>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v" into library work
Parsing module <bclk_dll>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/clk_dll/clk_dll.v" into library work
Parsing module <clk_dll>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/dcm_delay/dcm_delay.v" into library work
Parsing module <dcm_delay>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" into library work
Parsing module <novena_fpga>.
=========================================================================
* HDL Elaboration *
=========================================================================
WARNING:HDLCompiler:1016 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 430: Port clk133_p90 is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 434: Port clk133_p90 is not connected to this instance
Elaborating module <novena_fpga>.
Elaborating module <sync_reset>.
Elaborating module <FDPE>.
Elaborating module <IBUFG>.
Elaborating module <BUFG>.
Elaborating module <bclk_dll>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=2,CLKFX_MULTIPLY=2,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=7.518,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="NONE",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v" Line 112: Assignment to clk0 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v" Line 128: Assignment to status_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 424: Assignment to bclk_locked ignored, since the identifier is never used
Elaborating module <dcm_delay>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=1,CLKFX_MULTIPLY=4,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=7.518,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="1X",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/dcm_delay/dcm_delay.v" Line 137: Assignment to status_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 431: Assignment to i_fbk_out ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 432: Assignment to i_locked ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 435: Assignment to o_fbk_out ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 436: Assignment to o_locked ignored, since the identifier is never used
Elaborating module <BUFIO2FB>.
Elaborating module <clk_dll>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=1,CLKFX_MULTIPLY=4,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=20.0,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="1X",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/clk_dll/clk_dll.v" Line 135: Assignment to status_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 455: Assignment to clk25 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 459: Assignment to dll_locked ignored, since the identifier is never used
Elaborating module <FDSE>.
WARNING:HDLCompiler:413 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 490: Result of 25-bit expression is truncated to fit in 24-bit target.
Elaborating module <IBUFGDS>.
Elaborating module <IOBUF(DRIVE=12,SLEW="FAST")>.
Elaborating module <coretest_hashes>.
Elaborating module <sha1>.
Elaborating module <sha1_core>.
Elaborating module <sha1_w_mem>.
Elaborating module <sha256>.
Elaborating module <sha256_core>.
Elaborating module <sha256_k_constants>.
Elaborating module <sha256_w_mem>.
Elaborating module <sha512>.
Elaborating module <sha512_core>.
Elaborating module <sha512_k_constants>.
Elaborating module <sha512_h_constants>.
Elaborating module <sha512_w_mem>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <novena_fpga>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v".
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 423: Output port <LOCKED> of the instance <bclk_dll_mod> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <clk133_p90> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <clk133_p180> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <clk133_p270> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <CLKFB_OUT> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <LOCKED> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <clk133_p90> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <clk133_p180> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <clk133_p270> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <CLKFB_OUT> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <LOCKED> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 450: Output port <clk25> of the instance <clk_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 450: Output port <LOCKED> of the instance <clk_dll> is unconnected or connected to loadless signal.
Found 1-bit register for signal <rw_in>.
Found 16-bit register for signal <din_in>.
Found 1-bit register for signal <adv_in>.
Found 3-bit register for signal <a_in>.
Found 1-bit register for signal <cs0_r>.
Found 1-bit register for signal <rw_r>.
Found 16-bit register for signal <din_r>.
Found 1-bit register for signal <adv_r>.
Found 19-bit register for signal <bus_addr_r>.
Found 16-bit register for signal <ro_d_r>.
Found 2-bit register for signal <eim_rdcs>.
Found 16-bit register for signal <eim_dout_pipe>.
Found 16-bit register for signal <eim_dout_pipe2>.
Found 24-bit register for signal <counter>.
Found 1-bit register for signal <eim_lba_reg>.
Found 1-bit register for signal <eim_oe_reg>.
Found 16-bit register for signal <eim_d_t>.
Found 1-bit register for signal <cs0_in>.
Found 24-bit adder for signal <counter[23]_GND_1_o_add_16_OUT> created at line 490.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 152 D-type flip-flop(s).
Unit <novena_fpga> synthesized.
Synthesizing Unit <sync_reset>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/common/sync_reset.v".
Summary:
no macro.
Unit <sync_reset> synthesized.
Synthesizing Unit <bclk_dll>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v".
Summary:
no macro.
Unit <bclk_dll> synthesized.
Synthesizing Unit <dcm_delay>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/dcm_delay/dcm_delay.v".
Summary:
no macro.
Unit <dcm_delay> synthesized.
Synthesizing Unit <clk_dll>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/clk_dll/clk_dll.v".
Summary:
no macro.
Unit <clk_dll> synthesized.
Synthesizing Unit <coretest_hashes>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v".
SHA1_ADDR_PREFIX = 7'b1000010
SHA256_ADDR_PREFIX = 7'b1000011
SHA512_ADDR_PREFIX = 7'b1000100
WARNING:Xst:647 - Input <address<11:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" line 108: Output port <error> of the instance <sha1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" line 125: Output port <error> of the instance <sha256> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" line 142: Output port <error> of the instance <sha512> is unconnected or connected to loadless signal.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Found 1-bit tristate buffer for signal <read_data<15>> created at line 164
Found 1-bit tristate buffer for signal <read_data<14>> created at line 164
Found 1-bit tristate buffer for signal <read_data<13>> created at line 164
Found 1-bit tristate buffer for signal <read_data<12>> created at line 164
Found 1-bit tristate buffer for signal <read_data<11>> created at line 164
Found 1-bit tristate buffer for signal <read_data<10>> created at line 164
Found 1-bit tristate buffer for signal <read_data<9>> created at line 164
Found 1-bit tristate buffer for signal <read_data<8>> created at line 164
Found 1-bit tristate buffer for signal <read_data<7>> created at line 164
Found 1-bit tristate buffer for signal <read_data<6>> created at line 164
Found 1-bit tristate buffer for signal <read_data<5>> created at line 164
Found 1-bit tristate buffer for signal <read_data<4>> created at line 164
Found 1-bit tristate buffer for signal <read_data<3>> created at line 164
Found 1-bit tristate buffer for signal <read_data<2>> created at line 164
Found 1-bit tristate buffer for signal <read_data<1>> created at line 164
Found 1-bit tristate buffer for signal <read_data<0>> created at line 164
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 32 Latch(s).
inferred 46 Multiplexer(s).
inferred 16 Tristate(s).
Unit <coretest_hashes> synthesized.
Synthesizing Unit <sha1>.
Related source file is "/home/pselkirk/coretest/core/sha1/src/rtl/sha1.v".
ADDR_NAME0 = 8'b00000000
ADDR_NAME1 = 8'b00000001
ADDR_VERSION = 8'b00000010
ADDR_CTRL = 8'b00001000
CTRL_INIT_BIT = 0
CTRL_NEXT_BIT = 1
ADDR_STATUS = 8'b00001001
STATUS_READY_BIT = 0
STATUS_VALID_BIT = 1
ADDR_BLOCK0 = 8'b00010000
ADDR_BLOCK1 = 8'b00010001
ADDR_BLOCK2 = 8'b00010010
ADDR_BLOCK3 = 8'b00010011
ADDR_BLOCK4 = 8'b00010100
ADDR_BLOCK5 = 8'b00010101
ADDR_BLOCK6 = 8'b00010110
ADDR_BLOCK7 = 8'b00010111
ADDR_BLOCK8 = 8'b00011000
ADDR_BLOCK9 = 8'b00011001
ADDR_BLOCK10 = 8'b00011010
ADDR_BLOCK11 = 8'b00011011
ADDR_BLOCK12 = 8'b00011100
ADDR_BLOCK13 = 8'b00011101
ADDR_BLOCK14 = 8'b00011110
ADDR_BLOCK15 = 8'b00011111
ADDR_DIGEST0 = 8'b00100000
ADDR_DIGEST1 = 8'b00100001
ADDR_DIGEST2 = 8'b00100010
ADDR_DIGEST3 = 8'b00100011
ADDR_DIGEST4 = 8'b00100100
CORE_NAME0 = 32'b01110011011010000110000100110001
CORE_NAME1 = 32'b00100000001000000010000000100000
CORE_VERSION = 32'b00110000001011100011010100110000
Found 1-bit register for signal <next_reg>.
Found 1-bit register for signal <ready_reg>.
Found 160-bit register for signal <digest_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 32-bit register for signal <block0_reg>.
Found 32-bit register for signal <block1_reg>.
Found 32-bit register for signal <block2_reg>.
Found 32-bit register for signal <block3_reg>.
Found 32-bit register for signal <block4_reg>.
Found 32-bit register for signal <block5_reg>.
Found 32-bit register for signal <block6_reg>.
Found 32-bit register for signal <block7_reg>.
Found 32-bit register for signal <block8_reg>.
Found 32-bit register for signal <block9_reg>.
Found 32-bit register for signal <block10_reg>.
Found 32-bit register for signal <block11_reg>.
Found 32-bit register for signal <block12_reg>.
Found 32-bit register for signal <block13_reg>.
Found 32-bit register for signal <block14_reg>.
Found 32-bit register for signal <block15_reg>.
Found 1-bit register for signal <init_reg>.
Summary:
inferred 676 D-type flip-flop(s).
inferred 44 Multiplexer(s).
Unit <sha1> synthesized.
Synthesizing Unit <sha1_core>.
Related source file is "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_core.v".
H0_0 = 32'b01100111010001010010001100000001
H0_1 = 32'b11101111110011011010101110001001
H0_2 = 32'b10011000101110101101110011111110
H0_3 = 32'b00010000001100100101010001110110
H0_4 = 32'b11000011110100101110000111110000
SHA1_ROUNDS = 79
CTRL_IDLE = 0
CTRL_ROUNDS = 1
CTRL_DONE = 2
Found 32-bit register for signal <b_reg>.
Found 32-bit register for signal <c_reg>.
Found 32-bit register for signal <d_reg>.
Found 32-bit register for signal <e_reg>.
Found 32-bit register for signal <H0_reg>.
Found 32-bit register for signal <H1_reg>.
Found 32-bit register for signal <H2_reg>.
Found 32-bit register for signal <H3_reg>.
Found 32-bit register for signal <H4_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 7-bit register for signal <round_ctr_reg>.
Found 2-bit register for signal <sha1_ctrl_reg>.
Found 32-bit register for signal <a_reg>.
Found finite state machine <FSM_0> for signal <sha1_ctrl_reg>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 9 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | clk (rising_edge) |
| Reset | reset_n_INV_23_o (positive) |
| Reset type | synchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 32-bit adder for signal <H0_reg[31]_a_reg[31]_add_43_OUT> created at line 240.
Found 32-bit adder for signal <H1_reg[31]_b_reg[31]_add_44_OUT> created at line 241.
Found 32-bit adder for signal <H2_reg[31]_c_reg[31]_add_45_OUT> created at line 242.
Found 32-bit adder for signal <H3_reg[31]_d_reg[31]_add_46_OUT> created at line 243.
Found 32-bit adder for signal <H4_reg[31]_e_reg[31]_add_47_OUT> created at line 244.
Found 32-bit adder for signal <n0247> created at line 320.
Found 32-bit adder for signal <n0250> created at line 320.
Found 32-bit adder for signal <n0253> created at line 320.
Found 32-bit adder for signal <a_reg[26]_w[31]_add_93_OUT> created at line 320.
Found 7-bit adder for signal <round_ctr_reg[6]_GND_18_o_add_103_OUT> created at line 351.
Found 1-bit 4-to-1 multiplexer for signal <sha1_ctrl_we> created at line 378.
Found 7-bit comparator lessequal for signal <n0068> created at line 298
Found 7-bit comparator lessequal for signal <n0074> created at line 303
Found 7-bit comparator lessequal for signal <n0076> created at line 303
Found 7-bit comparator lessequal for signal <n0079> created at line 308
Found 7-bit comparator lessequal for signal <n0081> created at line 308
Found 7-bit comparator lessequal for signal <n0089> created at line 313
Summary:
inferred 10 Adder/Subtractor(s).
inferred 328 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 29 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <sha1_core> synthesized.
Synthesizing Unit <sha1_w_mem>.
Related source file is "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_w_mem.v".
SHA1_ROUNDS = 79
CTRL_IDLE = 1'b0
CTRL_UPDATE = 1'b1
Found 7-bit register for signal <w_ctr_reg>.
Found 1-bit register for signal <sha1_w_mem_ctrl_reg>.
Found 512-bit register for signal <n0061[511:0]>.
Found 7-bit adder for signal <w_ctr_reg[6]_GND_19_o_add_52_OUT> created at line 296.
Found 32-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][31]_wide_mux_9_OUT> created at line 185.
Found 7-bit comparator greater for signal <w_ctr_reg[6]_GND_19_o_LessThan_9_o> created at line 183
Found 7-bit comparator greater for signal <GND_19_o_w_ctr_reg[6]_LessThan_15_o> created at line 254
Summary:
inferred 1 Adder/Subtractor(s).
inferred 520 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 40 Multiplexer(s).
Unit <sha1_w_mem> synthesized.
Synthesizing Unit <sha256>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256.v".
ADDR_NAME0 = 8'b00000000
ADDR_NAME1 = 8'b00000001
ADDR_VERSION = 8'b00000010
ADDR_CTRL = 8'b00001000
CTRL_INIT_BIT = 0
CTRL_NEXT_BIT = 1
ADDR_STATUS = 8'b00001001
STATUS_READY_BIT = 0
STATUS_VALID_BIT = 1
ADDR_BLOCK0 = 8'b00010000
ADDR_BLOCK1 = 8'b00010001
ADDR_BLOCK2 = 8'b00010010
ADDR_BLOCK3 = 8'b00010011
ADDR_BLOCK4 = 8'b00010100
ADDR_BLOCK5 = 8'b00010101
ADDR_BLOCK6 = 8'b00010110
ADDR_BLOCK7 = 8'b00010111
ADDR_BLOCK8 = 8'b00011000
ADDR_BLOCK9 = 8'b00011001
ADDR_BLOCK10 = 8'b00011010
ADDR_BLOCK11 = 8'b00011011
ADDR_BLOCK12 = 8'b00011100
ADDR_BLOCK13 = 8'b00011101
ADDR_BLOCK14 = 8'b00011110
ADDR_BLOCK15 = 8'b00011111
ADDR_DIGEST0 = 8'b00100000
ADDR_DIGEST1 = 8'b00100001
ADDR_DIGEST2 = 8'b00100010
ADDR_DIGEST3 = 8'b00100011
ADDR_DIGEST4 = 8'b00100100
ADDR_DIGEST5 = 8'b00100101
ADDR_DIGEST6 = 8'b00100110
ADDR_DIGEST7 = 8'b00100111
CORE_NAME0 = 32'b01110011011010000110000100110010
CORE_NAME1 = 32'b00101101001100100011010100110110
CORE_VERSION = 32'b00110000001011100011100000110000
Found 1-bit register for signal <next_reg>.
Found 1-bit register for signal <ready_reg>.
Found 256-bit register for signal <digest_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 32-bit register for signal <block0_reg>.
Found 32-bit register for signal <block1_reg>.
Found 32-bit register for signal <block2_reg>.
Found 32-bit register for signal <block3_reg>.
Found 32-bit register for signal <block4_reg>.
Found 32-bit register for signal <block5_reg>.
Found 32-bit register for signal <block6_reg>.
Found 32-bit register for signal <block7_reg>.
Found 32-bit register for signal <block8_reg>.
Found 32-bit register for signal <block9_reg>.
Found 32-bit register for signal <block10_reg>.
Found 32-bit register for signal <block11_reg>.
Found 32-bit register for signal <block12_reg>.
Found 32-bit register for signal <block13_reg>.
Found 32-bit register for signal <block14_reg>.
Found 32-bit register for signal <block15_reg>.
Found 1-bit register for signal <init_reg>.
Summary:
inferred 772 D-type flip-flop(s).
inferred 44 Multiplexer(s).
Unit <sha256> synthesized.
Synthesizing Unit <sha256_core>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_core.v".
H0_0 = 32'b01101010000010011110011001100111
H0_1 = 32'b10111011011001111010111010000101
H0_2 = 32'b00111100011011101111001101110010
H0_3 = 32'b10100101010011111111010100111010
H0_4 = 32'b01010001000011100101001001111111
H0_5 = 32'b10011011000001010110100010001100
H0_6 = 32'b00011111100000111101100110101011
H0_7 = 32'b01011011111000001100110100011001
SHA256_ROUNDS = 63
CTRL_IDLE = 0
CTRL_ROUNDS = 1
CTRL_DONE = 2
Found 32-bit register for signal <b_reg>.
Found 32-bit register for signal <c_reg>.
Found 32-bit register for signal <d_reg>.
Found 32-bit register for signal <e_reg>.
Found 32-bit register for signal <f_reg>.
Found 32-bit register for signal <g_reg>.
Found 32-bit register for signal <h_reg>.
Found 32-bit register for signal <H0_reg>.
Found 32-bit register for signal <H1_reg>.
Found 32-bit register for signal <H2_reg>.
Found 32-bit register for signal <H3_reg>.
Found 32-bit register for signal <H4_reg>.
Found 32-bit register for signal <H5_reg>.
Found 32-bit register for signal <H6_reg>.
Found 32-bit register for signal <H7_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 6-bit register for signal <t_ctr_reg>.
Found 2-bit register for signal <sha256_ctrl_reg>.
Found 32-bit register for signal <a_reg>.
Found finite state machine <FSM_1> for signal <sha256_ctrl_reg>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 9 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | clk (rising_edge) |
| Reset | reset_n_INV_63_o (positive) |
| Reset type | synchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 32-bit adder for signal <H0_reg[31]_a_reg[31]_add_64_OUT> created at line 290.
Found 32-bit adder for signal <H1_reg[31]_b_reg[31]_add_65_OUT> created at line 291.
Found 32-bit adder for signal <H2_reg[31]_c_reg[31]_add_66_OUT> created at line 292.
Found 32-bit adder for signal <H3_reg[31]_d_reg[31]_add_67_OUT> created at line 293.
Found 32-bit adder for signal <H4_reg[31]_e_reg[31]_add_68_OUT> created at line 294.
Found 32-bit adder for signal <H5_reg[31]_f_reg[31]_add_69_OUT> created at line 295.
Found 32-bit adder for signal <H6_reg[31]_g_reg[31]_add_70_OUT> created at line 296.
Found 32-bit adder for signal <H7_reg[31]_h_reg[31]_add_71_OUT> created at line 297.
Found 32-bit adder for signal <n0313> created at line 319.
Found 32-bit adder for signal <n0316> created at line 319.
Found 32-bit adder for signal <n0319> created at line 319.
Found 32-bit adder for signal <t1> created at line 319.
Found 32-bit adder for signal <t2> created at line 339.
Found 32-bit adder for signal <t1[31]_t2[31]_add_114_OUT> created at line 394.
Found 32-bit adder for signal <d_reg[31]_t1[31]_add_115_OUT> created at line 398.
Found 6-bit adder for signal <t_ctr_reg[5]_GND_21_o_add_124_OUT> created at line 426.
Found 1-bit 4-to-1 multiplexer for signal <sha256_ctrl_we> created at line 461.
Summary:
inferred 16 Adder/Subtractor(s).
inferred 519 D-type flip-flop(s).
inferred 39 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <sha256_core> synthesized.
Synthesizing Unit <sha256_k_constants>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_k_constants.v".
Found 64x32-bit Read Only RAM for signal <tmp_K>
Summary:
inferred 1 RAM(s).
Unit <sha256_k_constants> synthesized.
Synthesizing Unit <sha256_w_mem>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_w_mem.v".
CTRL_IDLE = 0
CTRL_UPDATE = 1
Found 6-bit register for signal <w_ctr_reg>.
Found 2-bit register for signal <sha256_w_mem_ctrl_reg>.
Found 512-bit register for signal <n0070[511:0]>.
Found 32-bit adder for signal <n0135> created at line 233.
Found 32-bit adder for signal <n0138> created at line 233.
Found 32-bit adder for signal <w_new> created at line 233.
Found 6-bit adder for signal <w_ctr_reg[5]_GND_23_o_add_58_OUT> created at line 296.
Found 32-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][31]_wide_mux_12_OUT> created at line 178.
Found 6-bit comparator greater for signal <w_ctr_reg[5]_GND_23_o_LessThan_12_o> created at line 176
Found 6-bit comparator greater for signal <GND_23_o_w_ctr_reg[5]_LessThan_22_o> created at line 255
Summary:
inferred 4 Adder/Subtractor(s).
inferred 520 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 39 Multiplexer(s).
Unit <sha256_w_mem> synthesized.
Synthesizing Unit <sha512>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512.v".
ADDR_NAME0 = 8'b00000000
ADDR_NAME1 = 8'b00000001
ADDR_VERSION = 8'b00000010
ADDR_CTRL = 8'b00001000
CTRL_INIT_BIT = 0
CTRL_NEXT_BIT = 1
CTRL_MODE_LOW_BIT = 2
CTRL_MODE_HIGH_BIT = 3
ADDR_STATUS = 8'b00001001
STATUS_READY_BIT = 0
STATUS_VALID_BIT = 1
ADDR_BLOCK0 = 8'b00010000
ADDR_BLOCK1 = 8'b00010001
ADDR_BLOCK2 = 8'b00010010
ADDR_BLOCK3 = 8'b00010011
ADDR_BLOCK4 = 8'b00010100
ADDR_BLOCK5 = 8'b00010101
ADDR_BLOCK6 = 8'b00010110
ADDR_BLOCK7 = 8'b00010111
ADDR_BLOCK8 = 8'b00011000
ADDR_BLOCK9 = 8'b00011001
ADDR_BLOCK10 = 8'b00011010
ADDR_BLOCK11 = 8'b00011011
ADDR_BLOCK12 = 8'b00011100
ADDR_BLOCK13 = 8'b00011101
ADDR_BLOCK14 = 8'b00011110
ADDR_BLOCK15 = 8'b00011111
ADDR_BLOCK16 = 8'b00100000
ADDR_BLOCK17 = 8'b00100001
ADDR_BLOCK18 = 8'b00100010
ADDR_BLOCK19 = 8'b00100011
ADDR_BLOCK20 = 8'b00100100
ADDR_BLOCK21 = 8'b00100101
ADDR_BLOCK22 = 8'b00100110
ADDR_BLOCK23 = 8'b00100111
ADDR_BLOCK24 = 8'b00101000
ADDR_BLOCK25 = 8'b00101001
ADDR_BLOCK26 = 8'b00101010
ADDR_BLOCK27 = 8'b00101011
ADDR_BLOCK28 = 8'b00101100
ADDR_BLOCK29 = 8'b00101101
ADDR_BLOCK30 = 8'b00101110
ADDR_BLOCK31 = 8'b00101111
ADDR_DIGEST0 = 8'b01000000
ADDR_DIGEST1 = 8'b01000001
ADDR_DIGEST2 = 8'b01000010
ADDR_DIGEST3 = 8'b01000011
ADDR_DIGEST4 = 8'b01000100
ADDR_DIGEST5 = 8'b01000101
ADDR_DIGEST6 = 8'b01000110
ADDR_DIGEST7 = 8'b01000111
ADDR_DIGEST8 = 8'b01001000
ADDR_DIGEST9 = 8'b01001001
ADDR_DIGEST10 = 8'b01001010
ADDR_DIGEST11 = 8'b01001011
ADDR_DIGEST12 = 8'b01001100
ADDR_DIGEST13 = 8'b01001101
ADDR_DIGEST14 = 8'b01001110
ADDR_DIGEST15 = 8'b01001111
CORE_NAME0 = 32'b01110011011010000110000100110010
CORE_NAME1 = 32'b00101101001101010011000100110010
CORE_VERSION = 32'b00110000001011100011100000110000
MODE_SHA_512_224 = 2'b00
MODE_SHA_512_256 = 2'b01
MODE_SHA_384 = 2'b10
MODE_SHA_512 = 2'b11
Found 2-bit register for signal <mode_reg>.
Found 512-bit register for signal <digest_reg>.
Found 32-bit register for signal <block0_reg>.
Found 32-bit register for signal <block1_reg>.
Found 32-bit register for signal <block2_reg>.
Found 32-bit register for signal <block3_reg>.
Found 32-bit register for signal <block4_reg>.
Found 32-bit register for signal <block5_reg>.
Found 32-bit register for signal <block6_reg>.
Found 32-bit register for signal <block7_reg>.
Found 32-bit register for signal <block8_reg>.
Found 32-bit register for signal <block9_reg>.
Found 32-bit register for signal <block10_reg>.
Found 32-bit register for signal <block11_reg>.
Found 32-bit register for signal <block12_reg>.
Found 32-bit register for signal <block13_reg>.
Found 32-bit register for signal <block14_reg>.
Found 32-bit register for signal <block15_reg>.
Found 32-bit register for signal <block16_reg>.
Found 32-bit register for signal <block17_reg>.
Found 32-bit register for signal <block18_reg>.
Found 32-bit register for signal <block19_reg>.
Found 32-bit register for signal <block20_reg>.
Found 32-bit register for signal <block21_reg>.
Found 32-bit register for signal <block22_reg>.
Found 32-bit register for signal <block23_reg>.
Found 32-bit register for signal <block24_reg>.
Found 32-bit register for signal <block25_reg>.
Found 32-bit register for signal <block26_reg>.
Found 32-bit register for signal <block27_reg>.
Found 32-bit register for signal <block28_reg>.
Found 32-bit register for signal <block29_reg>.
Found 32-bit register for signal <block30_reg>.
Found 32-bit register for signal <block31_reg>.
Found 1-bit register for signal <next_reg>.
Found 1-bit register for signal <ready_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 1-bit register for signal <init_reg>.
Summary:
inferred 1542 D-type flip-flop(s).
inferred 81 Multiplexer(s).
Unit <sha512> synthesized.
Synthesizing Unit <sha512_core>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_core.v".
SHA512_ROUNDS = 79
CTRL_IDLE = 0
CTRL_ROUNDS = 1
CTRL_DONE = 2
Found 64-bit register for signal <b_reg>.
Found 64-bit register for signal <c_reg>.
Found 64-bit register for signal <d_reg>.
Found 64-bit register for signal <e_reg>.
Found 64-bit register for signal <f_reg>.
Found 64-bit register for signal <g_reg>.
Found 64-bit register for signal <h_reg>.
Found 64-bit register for signal <H0_reg>.
Found 64-bit register for signal <H1_reg>.
Found 64-bit register for signal <H2_reg>.
Found 64-bit register for signal <H3_reg>.
Found 64-bit register for signal <H4_reg>.
Found 64-bit register for signal <H5_reg>.
Found 64-bit register for signal <H6_reg>.
Found 64-bit register for signal <H7_reg>.
Found 64-bit register for signal <a_reg>.
Found 7-bit register for signal <t_ctr_reg>.
Found 2-bit register for signal <sha512_ctrl_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found finite state machine <FSM_2> for signal <sha512_ctrl_reg>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 9 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | clk (rising_edge) |
| Reset | reset_n (negative) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 64-bit adder for signal <H0_reg[63]_a_reg[63]_add_45_OUT> created at line 305.
Found 64-bit adder for signal <H1_reg[63]_b_reg[63]_add_46_OUT> created at line 306.
Found 64-bit adder for signal <H2_reg[63]_c_reg[63]_add_47_OUT> created at line 307.
Found 64-bit adder for signal <H3_reg[63]_d_reg[63]_add_48_OUT> created at line 308.
Found 64-bit adder for signal <H4_reg[63]_e_reg[63]_add_49_OUT> created at line 309.
Found 64-bit adder for signal <H5_reg[63]_f_reg[63]_add_50_OUT> created at line 310.
Found 64-bit adder for signal <H6_reg[63]_g_reg[63]_add_51_OUT> created at line 311.
Found 64-bit adder for signal <H7_reg[63]_h_reg[63]_add_52_OUT> created at line 312.
Found 64-bit adder for signal <n0303> created at line 334.
Found 64-bit adder for signal <n0306> created at line 334.
Found 64-bit adder for signal <n0309> created at line 334.
Found 64-bit adder for signal <t1> created at line 334.
Found 64-bit adder for signal <t2> created at line 354.
Found 64-bit adder for signal <t1[63]_t2[63]_add_95_OUT> created at line 409.
Found 64-bit adder for signal <d_reg[63]_t1[63]_add_96_OUT> created at line 413.
Found 7-bit adder for signal <t_ctr_reg[6]_GND_25_o_add_105_OUT> created at line 441.
Found 1-bit 4-to-1 multiplexer for signal <sha512_ctrl_we> created at line 476.
Summary:
inferred 16 Adder/Subtractor(s).
inferred 1032 D-type flip-flop(s).
inferred 47 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <sha512_core> synthesized.
Synthesizing Unit <sha512_k_constants>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_k_constants.v".
Found 128x64-bit Read Only RAM for signal <tmp_K>
Summary:
inferred 1 RAM(s).
Unit <sha512_k_constants> synthesized.
Synthesizing Unit <sha512_h_constants>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_h_constants.v".
Found 4x512-bit Read Only RAM for signal <_n0037>
Summary:
inferred 1 RAM(s).
Unit <sha512_h_constants> synthesized.
Synthesizing Unit <sha512_w_mem>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_w_mem.v".
CTRL_IDLE = 1'b0
CTRL_UPDATE = 1'b1
Found 7-bit register for signal <w_ctr_reg>.
Found 1024-bit register for signal <n0061[1023:0]>.
Found 1-bit register for signal <sha512_w_mem_ctrl_reg>.
Found 64-bit adder for signal <n0120> created at line 234.
Found 64-bit adder for signal <n0123> created at line 234.
Found 64-bit adder for signal <w_new> created at line 234.
Found 7-bit adder for signal <w_ctr_reg[6]_GND_28_o_add_52_OUT> created at line 297.
Found 64-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][63]_wide_mux_6_OUT> created at line 179.
Found 7-bit comparator greater for signal <w_ctr_reg[6]_GND_28_o_LessThan_6_o> created at line 177
Found 7-bit comparator greater for signal <GND_28_o_w_ctr_reg[6]_LessThan_16_o> created at line 256
Summary:
inferred 4 Adder/Subtractor(s).
inferred 1032 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 40 Multiplexer(s).
Unit <sha512_w_mem> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 3
128x64-bit single-port Read Only RAM : 1
4x512-bit single-port Read Only RAM : 1
64x32-bit single-port Read Only RAM : 1
# Adders/Subtractors : 52
24-bit adder : 1
32-bit adder : 27
6-bit adder : 2
64-bit adder : 18
7-bit adder : 4
# Registers : 142
1-bit register : 25
1024-bit register : 1
16-bit register : 5
160-bit register : 2
19-bit register : 2
2-bit register : 3
24-bit register : 1
256-bit register : 2
32-bit register : 75
512-bit register : 3
6-bit register : 2
64-bit register : 17
7-bit register : 4
# Latches : 32
1-bit latch : 32
# Comparators : 12
6-bit comparator greater : 2
7-bit comparator greater : 4
7-bit comparator lessequal : 6
# Multiplexers : 449
1-bit 2-to-1 multiplexer : 228
1-bit 4-to-1 multiplexer : 3
2-bit 2-to-1 multiplexer : 3
32-bit 16-to-1 multiplexer : 2
32-bit 2-to-1 multiplexer : 131
6-bit 2-to-1 multiplexer : 2
64-bit 16-to-1 multiplexer : 1
64-bit 2-to-1 multiplexer : 73
7-bit 2-to-1 multiplexer : 3
8-bit 2-to-1 multiplexer : 3
# Tristates : 16
1-bit tristate buffer : 16
# FSMs : 3
# Xors : 28
32-bit xor2 : 16
32-bit xor4 : 1
64-bit xor2 : 11
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <novena_fpga>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <novena_fpga> synthesized (advanced).
Synthesizing (advanced) Unit <sha1_core>.
The following registers are absorbed into counter <round_ctr_reg>: 1 register on signal <round_ctr_reg>.
The following adders/subtractors are grouped into adder tree <Madd_a_reg[26]_w[31]_add_93_OUT1> :
<Madd_n0247> in block <sha1_core>, <Madd_n0250> in block <sha1_core>, <Madd_n0253> in block <sha1_core>, <Madd_a_reg[26]_w[31]_add_93_OUT> in block <sha1_core>.
Unit <sha1_core> synthesized (advanced).
Synthesizing (advanced) Unit <sha1_w_mem>.
The following registers are absorbed into counter <w_ctr_reg>: 1 register on signal <w_ctr_reg>.
Unit <sha1_w_mem> synthesized (advanced).
Synthesizing (advanced) Unit <sha256_core>.
The following registers are absorbed into counter <t_ctr_reg>: 1 register on signal <t_ctr_reg>.
The following adders/subtractors are grouped into adder tree <Madd_t11> :
<Madd_n0313> in block <sha256_core>, <Madd_n0316> in block <sha256_core>, <Madd_n0319> in block <sha256_core>, <Madd_t1> in block <sha256_core>.
Unit <sha256_core> synthesized (advanced).
Synthesizing (advanced) Unit <sha256_k_constants>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_tmp_K> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 32-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <addr> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <tmp_K> | |
-----------------------------------------------------------------------
Unit <sha256_k_constants> synthesized (advanced).
Synthesizing (advanced) Unit <sha256_w_mem>.
The following registers are absorbed into counter <w_ctr_reg>: 1 register on signal <w_ctr_reg>.
The following adders/subtractors are grouped into adder tree <Madd_w_new1> :
<Madd_n0135> in block <sha256_w_mem>, <Madd_n0138> in block <sha256_w_mem>, <Madd_w_new> in block <sha256_w_mem>.
Unit <sha256_w_mem> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_core>.
The following registers are absorbed into accumulator <H1_reg>: 1 register on signal <H1_reg>.
The following registers are absorbed into accumulator <H3_reg>: 1 register on signal <H3_reg>.
The following registers are absorbed into accumulator <H2_reg>: 1 register on signal <H2_reg>.
The following registers are absorbed into accumulator <H5_reg>: 1 register on signal <H5_reg>.
The following registers are absorbed into accumulator <H4_reg>: 1 register on signal <H4_reg>.
The following registers are absorbed into accumulator <H6_reg>: 1 register on signal <H6_reg>.
The following registers are absorbed into accumulator <H7_reg>: 1 register on signal <H7_reg>.
The following registers are absorbed into accumulator <H0_reg>: 1 register on signal <H0_reg>.
The following registers are absorbed into counter <t_ctr_reg>: 1 register on signal <t_ctr_reg>.
Unit <sha512_core> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_h_constants>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0037> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4-word x 512-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <mode> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <sha512_h_constants> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_k_constants>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_tmp_K> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 128-word x 64-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <addr> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <tmp_K> | |
-----------------------------------------------------------------------
Unit <sha512_k_constants> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_w_mem>.
The following registers are absorbed into counter <w_ctr_reg>: 1 register on signal <w_ctr_reg>.
Unit <sha512_w_mem> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 3
128x64-bit single-port distributed Read Only RAM : 1
4x512-bit single-port distributed Read Only RAM : 1
64x32-bit single-port distributed Read Only RAM : 1
# Adders/Subtractors : 26
32-bit adder : 16
64-bit adder : 10
# Adder Trees : 3
32-bit / 4-inputs adder tree : 1
32-bit / 5-inputs adder tree : 2
# Counters : 7
24-bit up counter : 1
6-bit up counter : 2
7-bit up counter : 4
# Accumulators : 8
64-bit up loadable accumulator : 8
# Registers : 6537
Flip-Flops : 6537
# Comparators : 12
6-bit comparator greater : 2
7-bit comparator greater : 4
7-bit comparator lessequal : 6
# Multiplexers : 592
1-bit 16-to-1 multiplexer : 128
1-bit 2-to-1 multiplexer : 260
1-bit 4-to-1 multiplexer : 3
2-bit 2-to-1 multiplexer : 3
32-bit 2-to-1 multiplexer : 130
64-bit 2-to-1 multiplexer : 65
8-bit 2-to-1 multiplexer : 3
# FSMs : 3
# Xors : 28
32-bit xor2 : 16
32-bit xor4 : 1
64-bit xor2 : 11
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <sha256_w_mem_ctrl_reg_1> (without init value) has a constant value of 0 in block <sha256_w_mem>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <eim_d_t_0> in Unit <novena_fpga> is equivalent to the following 15 FFs/Latches, which will be removed : <eim_d_t_1> <eim_d_t_2> <eim_d_t_3> <eim_d_t_4> <eim_d_t_5> <eim_d_t_6> <eim_d_t_7> <eim_d_t_8> <eim_d_t_9> <eim_d_t_10> <eim_d_t_11> <eim_d_t_12> <eim_d_t_13> <eim_d_t_14> <eim_d_t_15>
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <core/sha1/core/FSM_0> on signal <sha1_ctrl_reg[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <core/sha256/core/FSM_1> on signal <sha256_ctrl_reg[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <core/sha512/core/FSM_2> on signal <sha512_ctrl_reg[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
WARNING:Xst:2042 - Unit coretest_hashes: 16 internal tristates are replaced by logic (pull-up yes): read_data<0>, read_data<10>, read_data<11>, read_data<12>, read_data<13>, read_data<14>, read_data<15>, read_data<1>, read_data<2>, read_data<3>, read_data<4>, read_data<5>, read_data<6>, read_data<7>, read_data<8>, read_data<9>.
Optimizing unit <novena_fpga> ...
Optimizing unit <coretest_hashes> ...
Optimizing unit <sha1> ...
Optimizing unit <sha1_core> ...
Optimizing unit <sha1_w_mem> ...
Optimizing unit <sha256> ...
Optimizing unit <sha256_core> ...
Optimizing unit <sha256_w_mem> ...
Optimizing unit <sha512> ...
Optimizing unit <sha512_core> ...
Optimizing unit <sha512_w_mem> ...
WARNING:Xst:2677 - Node <bus_addr_r_10> of sequential type is unconnected in block <novena_fpga>.
WARNING:Xst:2677 - Node <bus_addr_r_11> of sequential type is unconnected in block <novena_fpga>.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block novena_fpga, actual ratio is 50.
FlipFlop bus_addr_r_12 has been replicated 2 time(s)
FlipFlop core/sha1/init_reg has been replicated 1 time(s)
FlipFlop core/sha1/next_reg has been replicated 1 time(s)
FlipFlop core/sha256/core/sha256_ctrl_reg_FSM_FFd1 has been replicated 1 time(s)
FlipFlop core/sha256/init_reg has been replicated 1 time(s)
FlipFlop core/sha256/next_reg has been replicated 1 time(s)
FlipFlop core/sha512/core/digest_valid_reg has been replicated 1 time(s)
FlipFlop core/sha512/core/sha512_ctrl_reg_FSM_FFd1 has been replicated 2 time(s)
FlipFlop core/sha512/core/sha512_ctrl_reg_FSM_FFd2 has been replicated 1 time(s)
FlipFlop core/sha512/init_reg has been replicated 2 time(s)
FlipFlop core/sha512/next_reg has been replicated 2 time(s)
Final Macro Processing ...
Processing Unit <novena_fpga> :
Found 2-bit shift register for signal <din_r_10>.
Found 2-bit shift register for signal <din_r_11>.
Found 2-bit shift register for signal <rw_r>.
Found 2-bit shift register for signal <cs0_r>.
Unit <novena_fpga> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 7108
Flip-Flops : 7108
# Shift Registers : 4
2-bit shift register : 4
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : novena_eim.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 12770
# BUF : 13
# GND : 1
# INV : 4
# LUT1 : 23
# LUT2 : 1344
# LUT3 : 951
# LUT4 : 865
# LUT5 : 461
# LUT6 : 5512
# MUXCY : 1556
# MUXF7 : 319
# MUXF8 : 128
# VCC : 1
# XORCY : 1592
# FlipFlops/Latches : 7144
# FD : 95
# FDC : 16
# FDCE : 3598
# FDE : 23
# FDP : 4
# FDPE : 2
# FDR : 36
# FDRE : 3322
# FDSE : 16
# LDE : 16
# LDE_1 : 16
# Shift Registers : 4
# SRLC16E : 4
# Clock Buffers : 14
# BUFG : 14
# IO Buffers : 29
# IBUF : 9
# IBUFG : 1
# IBUFGDS : 1
# IOBUF : 16
# OBUF : 2
# DCMs : 4
# DCM_SP : 4
# Others : 1
# BUFIO2FB : 1
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-3
Slice Logic Utilization:
Number of Slice Registers: 7144 out of 54576 13%
Number of Slice LUTs: 9164 out of 27288 33%
Number used as Logic: 9160 out of 27288 33%
Number used as Memory: 4 out of 6408 0%
Number used as SRL: 4
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 12945
Number with an unused Flip Flop: 5801 out of 12945 44%
Number with an unused LUT: 3781 out of 12945 29%
Number of fully used LUT-FF pairs: 3363 out of 12945 25%
Number of unique control sets: 122
IO Utilization:
Number of IOs: 30
Number of bonded IOBs: 30 out of 218 13%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 14 out of 16 87%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-------------------------------------------------------------+---------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-------------------------------------------------------------+---------------------------+-------+
EIM_BCLK | DCM_SP:CLKFX | 7088 |
CLK2_P | DCM_SP:CLK0 | 24 |
core/cs_we_AND_247_o(core/cs_we_AND_247_o1:O) | NONE(*)(core/write_reg_16)| 16 |
core/cs_address[1]_AND_248_o(core/cs_address[1]_AND_248_o1:O)| NONE(*)(core/write_reg_0) | 16 |
CLK2_P | DCM_SP:CLK2X | 4 |
-------------------------------------------------------------+---------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 11.468ns (Maximum Frequency: 87.201MHz)
Minimum input arrival time before clock: 3.119ns
Maximum output required time after clock: 4.022ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'EIM_BCLK'
Clock period: 11.468ns (frequency: 87.201MHz)
Total number of paths / destination ports: 3205486019 / 14026
-------------------------------------------------------------------------
Delay: 11.468ns (Levels of Logic = 73)
Source: core/sha512/core/w_mem/w_mem_15_898 (FF)
Destination: core/sha512/core/a_reg_63 (FF)
Source Clock: EIM_BCLK rising
Destination Clock: EIM_BCLK rising
Data Path: core/sha512/core/w_mem/w_mem_15_898 to core/sha512/core/a_reg_63
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 4 0.447 0.912 core/sha512/core/w_mem/w_mem_15_898 (core/sha512/core/w_mem/w_mem_15_898)
LUT3:I0->O 2 0.205 0.721 core/sha512/core/w_mem/w_mem_update_logic.d0<1>1 (core/sha512/core/w_mem/w_mem_update_logic.d0<1>)
LUT3:I1->O 1 0.203 0.580 core/sha512/core/w_mem/Madd_n01231 (core/sha512/core/w_mem/Madd_n01231)
LUT4:I3->O 1 0.205 0.000 core/sha512/core/w_mem/Madd_n0123_lut<0>2 (core/sha512/core/w_mem/Madd_n0123_lut<0>2)
MUXCY:S->O 1 0.172 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_1 (core/sha512/core/w_mem/Madd_n0123_cy<0>2)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_2 (core/sha512/core/w_mem/Madd_n0123_cy<0>3)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_3 (core/sha512/core/w_mem/Madd_n0123_cy<0>4)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_4 (core/sha512/core/w_mem/Madd_n0123_cy<0>5)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_5 (core/sha512/core/w_mem/Madd_n0123_cy<0>6)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_6 (core/sha512/core/w_mem/Madd_n0123_cy<0>7)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_7 (core/sha512/core/w_mem/Madd_n0123_cy<0>8)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_8 (core/sha512/core/w_mem/Madd_n0123_cy<0>9)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_9 (core/sha512/core/w_mem/Madd_n0123_cy<0>10)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_10 (core/sha512/core/w_mem/Madd_n0123_cy<0>11)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_11 (core/sha512/core/w_mem/Madd_n0123_cy<0>12)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_12 (core/sha512/core/w_mem/Madd_n0123_cy<0>13)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_13 (core/sha512/core/w_mem/Madd_n0123_cy<0>14)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_14 (core/sha512/core/w_mem/Madd_n0123_cy<0>15)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_15 (core/sha512/core/w_mem/Madd_n0123_cy<0>16)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_16 (core/sha512/core/w_mem/Madd_n0123_cy<0>17)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_17 (core/sha512/core/w_mem/Madd_n0123_cy<0>18)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_18 (core/sha512/core/w_mem/Madd_n0123_cy<0>19)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_19 (core/sha512/core/w_mem/Madd_n0123_cy<0>20)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_20 (core/sha512/core/w_mem/Madd_n0123_cy<0>21)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_21 (core/sha512/core/w_mem/Madd_n0123_cy<0>22)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_22 (core/sha512/core/w_mem/Madd_n0123_cy<0>23)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_23 (core/sha512/core/w_mem/Madd_n0123_cy<0>24)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_24 (core/sha512/core/w_mem/Madd_n0123_cy<0>25)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_25 (core/sha512/core/w_mem/Madd_n0123_cy<0>26)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_26 (core/sha512/core/w_mem/Madd_n0123_cy<0>27)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_27 (core/sha512/core/w_mem/Madd_n0123_cy<0>28)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_28 (core/sha512/core/w_mem/Madd_n0123_cy<0>29)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_29 (core/sha512/core/w_mem/Madd_n0123_cy<0>30)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_30 (core/sha512/core/w_mem/Madd_n0123_cy<0>31)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_31 (core/sha512/core/w_mem/Madd_n0123_cy<0>32)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_32 (core/sha512/core/w_mem/Madd_n0123_cy<0>33)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_33 (core/sha512/core/w_mem/Madd_n0123_cy<0>34)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_34 (core/sha512/core/w_mem/Madd_n0123_cy<0>35)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_35 (core/sha512/core/w_mem/Madd_n0123_cy<0>36)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_36 (core/sha512/core/w_mem/Madd_n0123_cy<0>37)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_37 (core/sha512/core/w_mem/Madd_n0123_cy<0>38)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_38 (core/sha512/core/w_mem/Madd_n0123_cy<0>39)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_39 (core/sha512/core/w_mem/Madd_n0123_cy<0>40)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_40 (core/sha512/core/w_mem/Madd_n0123_cy<0>41)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_41 (core/sha512/core/w_mem/Madd_n0123_cy<0>42)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_42 (core/sha512/core/w_mem/Madd_n0123_cy<0>43)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_43 (core/sha512/core/w_mem/Madd_n0123_cy<0>44)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_44 (core/sha512/core/w_mem/Madd_n0123_cy<0>45)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_45 (core/sha512/core/w_mem/Madd_n0123_cy<0>46)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_46 (core/sha512/core/w_mem/Madd_n0123_cy<0>47)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_47 (core/sha512/core/w_mem/Madd_n0123_cy<0>48)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_48 (core/sha512/core/w_mem/Madd_n0123_cy<0>49)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_49 (core/sha512/core/w_mem/Madd_n0123_cy<0>50)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_50 (core/sha512/core/w_mem/Madd_n0123_cy<0>51)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_51 (core/sha512/core/w_mem/Madd_n0123_cy<0>52)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_52 (core/sha512/core/w_mem/Madd_n0123_cy<0>53)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_53 (core/sha512/core/w_mem/Madd_n0123_cy<0>54)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_54 (core/sha512/core/w_mem/Madd_n0123_cy<0>55)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_55 (core/sha512/core/w_mem/Madd_n0123_cy<0>56)
MUXCY:CI->O 1 0.019 0.000 core/sha512/core/w_mem/Madd_n0123_cy<0>_56 (core/sha512/core/w_mem/Madd_n0123_cy<0>57)
XORCY:CI->O 1 0.180 0.580 core/sha512/core/w_mem/Madd_n0123_xor<0>_57 (core/sha512/core/w_mem/n0123<58>)
LUT3:I2->O 1 0.205 0.000 core/sha512/core/w_mem/Madd_w_new_lut<58> (core/sha512/core/w_mem/Madd_w_new_lut<58>)
MUXCY:S->O 1 0.172 0.000 core/sha512/core/w_mem/Madd_w_new_cy<58> (core/sha512/core/w_mem/Madd_w_new_cy<58>)
XORCY:CI->O 2 0.180 0.617 core/sha512/core/w_mem/Madd_w_new_xor<59> (core/sha512/core/w_mem/w_new<59>)
LUT5:I4->O 2 0.205 0.617 core/sha512/core/w_mem/Mmux_w_tmp551 (core/sha512/core/w_data<59>)
LUT3:I2->O 1 0.205 0.580 core/sha512/core/Madd_t159 (core/sha512/core/Madd_t159)
LUT4:I3->O 1 0.205 0.000 core/sha512/core/Madd_t1_lut<0>60 (core/sha512/core/Madd_t1_lut<0>60)
MUXCY:S->O 1 0.172 0.000 core/sha512/core/Madd_t1_cy<0>_59 (core/sha512/core/Madd_t1_cy<0>60)
XORCY:CI->O 3 0.180 0.651 core/sha512/core/Madd_t1_xor<0>_60 (core/sha512/core/t1<61>)
LUT3:I2->O 1 0.205 0.580 core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT61 (core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT61)
LUT4:I3->O 1 0.205 0.000 core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT_lut<0>62 (core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT_lut<0>62)
MUXCY:S->O 0 0.172 0.000 core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT_cy<0>_61 (core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT_cy<0>62)
XORCY:CI->O 1 0.180 0.580 core/sha512/core/Madd_t1[63]_t2[63]_add_95_OUT_xor<0>_62 (core/sha512/core/t1[63]_t2[63]_add_95_OUT<63>)
LUT6:I5->O 1 0.205 0.000 core/sha512/core/Mmux_a_h_we1601 (core/sha512/core/a_new<63>)
FDCE:D 0.102 core/sha512/core/a_reg_63
----------------------------------------
Total 11.468ns (5.050ns logic, 6.418ns route)
(44.0% logic, 56.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK2_P'
Clock period: 2.256ns (frequency: 443.321MHz)
Total number of paths / destination ports: 303 / 27
-------------------------------------------------------------------------
Delay: 1.128ns (Levels of Logic = 0)
Source: dll_res_sync/fdres2 (FF)
Destination: dll_res_sync/fdres3 (FF)
Source Clock: CLK2_P rising 2.0X
Destination Clock: CLK2_P rising 2.0X
Data Path: dll_res_sync/fdres2 to dll_res_sync/fdres3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDP:C->Q 1 0.447 0.579 dll_res_sync/fdres2 (dll_res_sync/reschain<2>)
FDP:D 0.102 dll_res_sync/fdres3
----------------------------------------
Total 1.128ns (0.549ns logic, 0.579ns route)
(48.7% logic, 51.3% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'EIM_BCLK'
Total number of paths / destination ports: 26 / 26
-------------------------------------------------------------------------
Offset: 2.725ns (Levels of Logic = 2)
Source: EIM_LBA (PAD)
Destination: adv_in (FF)
Destination Clock: EIM_BCLK rising
Data Path: EIM_LBA to adv_in
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.222 0.616 EIM_LBA_IBUF (EIM_LBA_IBUF)
INV:I->O 1 0.206 0.579 adv_in_rstpot1_INV_0 (adv_in_rstpot)
FD:D 0.102 adv_in
----------------------------------------
Total 2.725ns (1.530ns logic, 1.195ns route)
(56.1% logic, 43.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK2_P'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 3.119ns (Levels of Logic = 2)
Source: RESETBMCU (PAD)
Destination: dll_res_sync/fdres3 (FF)
Destination Clock: CLK2_P rising 2.0X
Data Path: RESETBMCU to dll_res_sync/fdres3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.222 0.579 RESETBMCU_IBUF (RESETBMCU_IBUF)
INV:I->O 4 0.206 0.683 RESETBMCU_INV_3_o1_INV_0 (RESETBMCU_INV_3_o)
FDP:PRE 0.430 dll_res_sync/fdres3
----------------------------------------
Total 3.119ns (1.858ns logic, 1.261ns route)
(59.6% logic, 40.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'EIM_BCLK'
Total number of paths / destination ports: 32 / 16
-------------------------------------------------------------------------
Offset: 4.022ns (Levels of Logic = 1)
Source: eim_d_t_0 (FF)
Destination: EIM_DA<15> (PAD)
Source Clock: EIM_BCLK rising
Data Path: eim_d_t_0 to EIM_DA<15>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 16 0.447 1.004 eim_d_t_0 (eim_d_t_0)
IOBUF:T->IO 2.571 IOBUF_eim0 (EIM_DA<0>)
----------------------------------------
Total 4.022ns (3.018ns logic, 1.004ns route)
(75.0% logic, 25.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK2_P'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.634ns (Levels of Logic = 1)
Source: counter_23 (FF)
Destination: FPGA_LED2 (PAD)
Source Clock: CLK2_P rising
Data Path: counter_23 to FPGA_LED2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.447 0.616 counter_23 (counter_23)
OBUF:I->O 2.571 FPGA_LED2_OBUF (FPGA_LED2)
----------------------------------------
Total 3.634ns (3.018ns logic, 0.616ns route)
(83.0% logic, 17.0% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock CLK2_P
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK2_P | 2.104| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock EIM_BCLK
----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
CLK2_P | 6.235| | | |
EIM_BCLK | 11.468| | | |
core/cs_address[1]_AND_248_o| 3.211| | | |
core/cs_we_AND_247_o | | 1.798| | |
----------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock core/cs_address[1]_AND_248_o
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
EIM_BCLK | 4.615| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock core/cs_we_AND_247_o
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
EIM_BCLK | | | 3.929| |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 52.00 secs
Total CPU time to Xst completion: 50.86 secs
-->
Total memory usage is 478652 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 51 ( 0 filtered)
Number of infos : 21 ( 0 filtered)
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; ngdbuild novena_eim.ngc -bm novena_eim.bmm
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - ngdbuild P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
novena_eim.ngc -bm novena_eim.bmm
Reading NGO file "/home/pselkirk/coretest/core/novena_eim/build/novena_eim.ngc"
...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "novena_eim.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'clk_tnm', used in period specification
'TS_clk', was traced into DCM_SP instance clk_dll/dcm_sp_inst. The following
new TNM groups and period specifications were generated at the DCM_SP
output(s):
CLK2X: <TIMESPEC TS_clk_dll_clk2x = PERIOD "clk_dll_clk2x" TS_clk * 2 HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'clk_tnm', used in period specification
'TS_clk', was traced into DCM_SP instance clk_dll/dcm_sp_inst. The following
new TNM groups and period specifications were generated at the DCM_SP
output(s):
CLK0: <TIMESPEC TS_clk_dll_clk0 = PERIOD "clk_dll_clk0" TS_clk HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'bclk_tnm', used in period specification
'TS_bclk', was traced into DCM_SP instance bclk_dll_mod/dcm_sp_inst. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLKFX: <TIMESPEC TS_bclk_dll_mod_clkfx = PERIOD "bclk_dll_mod_clkfx" TS_bclk
HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'bclk_tnm', used in period specification
'TS_bclk', was traced into DCM_SP instance bclk_o_dll/dcm_sp_inst. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK0: <TIMESPEC TS_bclk_o_dll_clk0 = PERIOD "bclk_o_dll_clk0" TS_bclk HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'bclk_tnm', used in period specification
'TS_bclk', was traced into DCM_SP instance bclk_i_dll/dcm_sp_inst. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK0: <TIMESPEC TS_bclk_i_dll_clk0 = PERIOD "bclk_i_dll_clk0" TS_bclk HIGH
50%>
INFO:ConstraintSystem - The Period constraint <NET "CLK2_P" PERIOD = 20 ns;>
[novena_eim.ucf(653)], is specified using the Net Period method which is not
recommended. Please use the Timespec PERIOD method.
Done...
Processing BMM file "novena_eim.bmm" ...
WARNING::53 - File 'novena_eim.bmm' is empty or has no BMM content.
WARNING:NgdBuild:1212 - User specified non-default attribute value (7.518000)
was detected for the CLKIN_PERIOD attribute on DCM
"bclk_dll_mod/dcm_sp_inst". This does not match the PERIOD constraint value
(133 MHz.). The uncertainty calculation will use the non-default attribute
value. This could result in incorrect uncertainty calculated for DCM output
clocks.
WARNING:NgdBuild:1212 - User specified non-default attribute value (7.518000)
was detected for the CLKIN_PERIOD attribute on DCM "bclk_o_dll/dcm_sp_inst".
This does not match the PERIOD constraint value (133 MHz.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
WARNING:NgdBuild:1212 - User specified non-default attribute value (7.518000)
was detected for the CLKIN_PERIOD attribute on DCM "bclk_i_dll/dcm_sp_inst".
This does not match the PERIOD constraint value (133 MHz.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 3
Writing NGD file "novena_eim.ngd" ...
Total REAL time to NGDBUILD completion: 8 sec
Total CPU time to NGDBUILD completion: 8 sec
Writing NGDBUILD log file "novena_eim.bld"...
NGDBUILD done.
if [ -r novena_eim_par.ncd ]; then \
cp novena_eim_par.ncd smartguide.ncd; \
smartguide="-smartguide smartguide.ncd"; \
else \
smartguide=""; \
fi; \
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
map -timing -ol high -detail -pr b -register_duplication -w $smartguide novena_eim.ngd
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - Map P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Using target part "6slx45csg324-3".
Mapping design into LUTs...
Writing file novena_eim.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3402 - The Clock Modifying COMP, bclk_dll_mod/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
FROM/TO constraints.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 24 secs
Total CPU time at the beginning of Placer: 24 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:516db9d5) REAL time: 27 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:516db9d5) REAL time: 28 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:516db9d5) REAL time: 28 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:68ddab6d) REAL time: 45 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:68ddab6d) REAL time: 45 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:68ddab6d) REAL time: 45 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:68ddab6d) REAL time: 45 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:68ddab6d) REAL time: 46 secs
Phase 9.8 Global Placement
..............................................................................................................................
...............................................................
............................................................................
.....................................
Phase 9.8 Global Placement (Checksum:ec3f7251) REAL time: 3 mins 19 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ec3f7251) REAL time: 3 mins 19 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1d25156d) REAL time: 3 mins 57 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1d25156d) REAL time: 3 mins 58 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:4f57fcf3) REAL time: 3 mins 58 secs
Total REAL time to Placer completion: 4 mins 9 secs
Total CPU time to Placer completion: 4 mins 8 secs
Running physical synthesis...
.
Physical synthesis completed.
Running post-placement packing...
Writing output files...
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_i_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_o_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found NO extern
Design Summary:
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 7,759 out of 54,576 14%
Number used as Flip Flops: 7,307
Number used as Latches: 32
Number used as Latch-thrus: 0
Number used as AND/OR logics: 420
Number of Slice LUTs: 8,694 out of 27,288 31%
Number used as logic: 8,594 out of 27,288 31%
Number using O6 output only: 7,731
Number using O5 output only: 22
Number using O5 and O6: 841
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 96
Number with same-slice register load: 95
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,111 out of 6,822 45%
Nummber of MUXCYs used: 1,592 out of 13,644 11%
Number of LUT Flip Flop pairs used: 10,283
Number with an unused Flip Flop: 2,773 out of 10,283 26%
Number with an unused LUT: 1,589 out of 10,283 15%
Number of fully used LUT-FF pairs: 5,921 out of 10,283 57%
Number of unique control sets: 196
Number of slice register sites lost
to control set restrictions: 409 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 30 out of 218 13%
Number of LOCed IOBs: 30 out of 30 100%
IOB Flip Flops: 37
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 4 out of 8 50%
Number used as DCMs: 4
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 21 out of 376 5%
Number used as ILOGIC2s: 21
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 16 out of 376 4%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.99
Peak Memory Usage: 993 MB
Total REAL time to MAP completion: 7 mins 45 secs
Total CPU time to MAP completion: 7 mins 43 secs
Mapping completed.
See MAP report file "novena_eim.mrp" for details.
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
if par -ol high -w novena_eim.ncd novena_eim_par.ncd; then \
:; \
else \
make etwr; \
fi
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - par P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Constraints file: novena_eim.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment /opt/Xilinx/14.3/ISE_DS/ISE/.
"novena_fpga" is an NCD, version 3.2, device xc6slx45, package csg324, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2012-10-12".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 7,759 out of 54,576 14%
Number used as Flip Flops: 7,307
Number used as Latches: 32
Number used as Latch-thrus: 0
Number used as AND/OR logics: 420
Number of Slice LUTs: 8,694 out of 27,288 31%
Number used as logic: 8,594 out of 27,288 31%
Number using O6 output only: 7,731
Number using O5 output only: 22
Number using O5 and O6: 841
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 96
Number with same-slice register load: 95
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,111 out of 6,822 45%
Nummber of MUXCYs used: 1,592 out of 13,644 11%
Number of LUT Flip Flop pairs used: 10,283
Number with an unused Flip Flop: 2,773 out of 10,283 26%
Number with an unused LUT: 1,589 out of 10,283 15%
Number of fully used LUT-FF pairs: 5,921 out of 10,283 57%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 30 out of 218 13%
Number of LOCed IOBs: 30 out of 30 100%
IOB Flip Flops: 37
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 7 out of 16 43%
Number used as BUFGs: 7
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 4 out of 8 50%
Number used as DCMs: 4
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 21 out of 376 5%
Number used as ILOGIC2s: 21
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 16 out of 376 4%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
WARNING:Timing:3402 - The Clock Modifying COMP, bclk_dll_mod/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
FROM/TO constraints.
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 14 secs
Starting Router
Phase 1 : 56136 unrouted; REAL time: 16 secs
Phase 2 : 52865 unrouted; REAL time: 19 secs
Phase 3 : 20631 unrouted; REAL time: 58 secs
Phase 4 : 24978 unrouted; (Setup:1104315, Hold:1821037, Component Switching Limit:0) REAL time: 1 mins 29 secs
Updating file: novena_eim_par.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:1056315, Hold:1204986, Component Switching Limit:0) REAL time: 6 mins 1 secs
Phase 6 : 0 unrouted; (Setup:1056315, Hold:1204986, Component Switching Limit:0) REAL time: 9 mins 35 secs
Phase 7 : 0 unrouted; (Setup:1056315, Hold:1204986, Component Switching Limit:0) REAL time: 10 mins 28 secs
Phase 8 : 0 unrouted; (Setup:1056315, Hold:1204986, Component Switching Limit:0) REAL time: 10 mins 28 secs
WARNING:Route:522 - Unusually high hold time violation detected among 10 connections.The router will continue and try to fix it
EIM_CS<1>:I -> eim_rdcs<1>:D -4232
EIM_CS<0>:I -> EIM_CS_0_IBUF:D -4126
din_r<15>:BQ -> core/sha1/block7_reg<31>:B6 -2335
din_r<7>:BQ -> core/sha1/block2_reg<7>:B6 -2092
cs0_r:AQ -> core/sha1/block1_reg<11>:C6 -2084
core/read_data<13>LogicTrst81:DMUX -> core/sha1/block1_reg<11>:C1 -2060
cs0_r:DQ -> N5:C3 -2059
N5:C -> core/sha1/block3_reg<11>:CE -2059
din_r<7>:BQ -> core/sha256/block9_reg<23>:B6 -2017
N5:C -> core/sha1/block3_reg<31>:CE -2005
Phase 9 : 0 unrouted; (Setup:1056185, Hold:620374, Component Switching Limit:0) REAL time: 19 mins 9 secs
Phase 10 : 0 unrouted; (Setup:1048869, Hold:620374, Component Switching Limit:0) REAL time: 19 mins 13 secs
Total REAL time to Router completion: 19 mins 13 secs
Total CPU time to Router completion: 19 mins 25 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| bclk_dll | BUFGMUX_X2Y12| No | 1887 | 0.506 | 1.717 |
+---------------------+--------------+------+------+------------+-------------+
| bclk_i | BUFGMUX_X2Y1| No | 129 | 0.530 | 1.744 |
+---------------------+--------------+------+------+------------+-------------+
| bclk_o | BUFGMUX_X2Y3| No | 22 | 0.519 | 1.735 |
+---------------------+--------------+------+------+------------+-------------+
| clk50 | BUFGMUX_X2Y4| No | 7 | 0.009 | 1.222 |
+---------------------+--------------+------+------+------------+-------------+
| slowclk | BUFGMUX_X3Y13| No | 1 | 0.000 | 1.268 |
+---------------------+--------------+------+------+------------+-------------+
|core/cs_address[1]_A | | | | | |
| ND_248_o | Local| | 95 | 1.089 | 2.116 |
+---------------------+--------------+------+------+------------+-------------+
|core/cs_we_AND_247_o | | | | | |
| | Local| | 64 | 0.848 | 2.613 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 1669243 (Setup: 1048869, Hold: 620374, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 5
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_bclk_dll_mod_clkfx = PERIOD TIMEGRP "b | SETUP | -7.255ns| 14.773ns| 279| 1038152
clk_dll_mod_clkfx" TS_bclk HIGH 50% | HOLD | -2.335ns| | 976| 587071
----------------------------------------------------------------------------------------------------------
* OFFSET = IN 4.125 ns VALID 4.75 ns BEFORE | SETUP | 0.494ns| 3.631ns| 0| 0
COMP "EIM_BCLK" | HOLD | -4.232ns| | 21| 33303
----------------------------------------------------------------------------------------------------------
* OFFSET = OUT 5.1 ns AFTER COMP "EIM_BCLK" | MAXDELAY | -0.710ns| 5.810ns| 16| 10717
----------------------------------------------------------------------------------------------------------
TS_bclk_o_dll_clk0 = PERIOD TIMEGRP "bclk | SETUP | 0.048ns| 7.470ns| 0| 0
_o_dll_clk0" TS_bclk HIGH 50% | HOLD | 1.276ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_bclk_i_dll_clk0 = PERIOD TIMEGRP "bclk | SETUP | 0.048ns| 7.470ns| 0| 0
_i_dll_clk0" TS_bclk HIGH 50% | HOLD | 0.944ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_bclk = PERIOD TIMEGRP "bclk_tnm" 133 M | MINLOWPULSE | 2.178ns| 5.340ns| 0| 0
Hz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "clk_dll/clk2x" d | SETUP | 8.403ns| 1.597ns| 0| 0
erived from NET "clk" PERIOD = 20 ns HIG | HOLD | 0.459ns| | 0| 0
H 50% | MINPERIOD | 7.330ns| 2.670ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk_tnm" 50 MHz | MINLOWPULSE | 12.000ns| 8.000ns| 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_dll_clk2x = PERIOD TIMEGRP "clk_dl | MINPERIOD | 8.270ns| 1.730ns| 0| 0
l_clk2x" TS_clk * 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "clk" PERIOD = 20 ns HIGH 50% | MINLOWPULSE | 12.000ns| 8.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "clk_dll/clk0" de | SETUP | 17.879ns| 2.121ns| 0| 0
rived from NET "clk" PERIOD = 20 ns HIGH | HOLD | 0.525ns| | 0| 0
50% | MINPERIOD | 16.430ns| 3.570ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_dll_clk0 = PERIOD TIMEGRP "clk_dll | MINPERIOD | 18.270ns| 1.730ns| 0| 0
_clk0" TS_clk HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|clk | 20.000ns| 8.000ns| 5.340ns| 0| 0| 0| 303|
| clk_dll/clk0 | 20.000ns| 3.570ns| N/A| 0| 0| 300| 0|
| clk_dll/clk2x | 10.000ns| 2.670ns| N/A| 0| 0| 3| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk | 20.000ns| 8.000ns| 3.460ns| 0| 0| 0| 0|
| TS_clk_dll_clk2x | 10.000ns| 1.730ns| N/A| 0| 0| 0| 0|
| TS_clk_dll_clk0 | 20.000ns| 1.730ns| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_bclk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_bclk | 7.519ns| 5.340ns| 14.773ns| 0| 1255| 0| 3205487365|
| TS_bclk_dll_mod_clkfx | 7.519ns| 14.773ns| N/A| 1255| 0| 3205487072| 0|
| TS_bclk_o_dll_clk0 | 7.519ns| 7.470ns| N/A| 0| 0| 34| 0|
| TS_bclk_i_dll_clk0 | 7.519ns| 7.470ns| N/A| 0| 0| 259| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3 constraints not met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 19 mins 17 secs
Total CPU time to PAR completion: 19 mins 30 secs
Peak Memory Usage: 943 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 1292 errors found.
Number of error messages: 0
Number of warning messages: 3
Number of info messages: 0
Writing design to file novena_eim_par.ncd
PAR done!
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
bitgen -g UnusedPin:Pullnone -g DriveDone:yes -g StartupClk:Cclk -w novena_eim_par.ncd novena_eim.bit
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - Bitgen P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45.nph' in environment
/opt/Xilinx/14.3/ISE_DS/ISE/.
"novena_fpga" is an NCD, version 3.2, device xc6slx45, package csg324, speed
-3
Thu Nov 6 14:31:47 2014
Running DRC.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_i_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_o_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found NO extern
WARNING:PhysDesignRules:372 - Gated clock. Clock net
core/cs_address[1]_AND_248_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net core/cs_we_AND_247_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp bclk_dll_mod/dcm_sp_inst,
consult the device Data Sheet.
DRC detected 0 errors and 2 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "novena_eim.bit".
Bitstream generation is complete.
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
promgen -w -s 8192 -p mcs -o novena_eim.mcs -u 0 novena_eim.bit
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - Promgen P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
0x16a674 (1484404) bytes loaded up from 0x0
Using user-specified prom size of 8192K
Writing file "novena_eim.mcs".
Writing file "novena_eim.prm".
Writing file "novena_eim.cfi".
real 28m56.380s
user 28m53.503s
sys 0m12.877s
-------------- next part --------------
tin-man:~/coretest/core/novena_eim/build$ time make
echo "run" > novena_eim.scr
echo "-p xc6slx45csg324-3" >> novena_eim.scr
echo "-top novena_fpga" >> novena_eim.scr
echo "-ifn novena_eim.prj" >> novena_eim.scr
echo "-ofn novena_eim.ngc" >> novena_eim.scr
cat ./xilinx.opt >> novena_eim.scr
for src in ../../sha1/src/rtl/sha1.v ../../sha1/src/rtl/sha1_core.v ../../sha1/src/rtl/sha1_w_mem.v ../../sha256/src/rtl/sha256.v ../../sha256/src/rtl/sha256_core.v ../../sha256/src/rtl/sha256_k_constants.v ../../sha256/src/rtl/sha256_w_mem.v ../../sha512/src/rtl/sha512.v ../../sha512/src/rtl/sha512_core.v ../../sha512/src/rtl/sha512_h_constants.v ../../sha512/src/rtl/sha512_k_constants.v ../../sha512/src/rtl/sha512_w_mem.v ../src/rtl/common/sync_reset.v ../src/rtl/coretest_hashes.v ../src/rtl/ip/bclk_dll/bclk_dll.v ../src/rtl/ip/clk_dll/clk_dll.v ../src/rtl/ip/dcm_delay/dcm_delay.v ../src/rtl/novena_fpga.v ; do echo "verilog work $src" >> novena_eim.tmpprj; done
sort -u novena_eim.tmpprj > novena_eim.prj
rm -f novena_eim.tmpprj
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; xst -ifn novena_eim.scr
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - xst P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "novena_eim.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Target Device : xc6slx45csg324-3
Output File Name : "novena_eim.ngc"
Output Format : NGC
---- Source Options
Top Module Name : novena_fpga
Safe Implementation : No
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
ROM Style : Auto
Shift Register Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Keep Hierarchy : no
Netlist Hierarchy : as_optimized
RTL Output : no
Global Optimization : AllClockNets
Read Cores : yes
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_core.v" into library work
Parsing module <sha1_core>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha1/src/rtl/sha1.v" into library work
Parsing module <sha1>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_w_mem.v" into library work
Parsing module <sha1_w_mem>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_core.v" into library work
Parsing module <sha256_core>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_k_constants.v" into library work
Parsing module <sha256_k_constants>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256.v" into library work
Parsing module <sha256>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_w_mem.v" into library work
Parsing module <sha256_w_mem>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_core.v" into library work
Parsing module <sha512_core>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_h_constants.v" into library work
Parsing module <sha512_h_constants>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_k_constants.v" into library work
Parsing module <sha512_k_constants>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512.v" into library work
Parsing module <sha512>.
Analyzing Verilog file "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_w_mem.v" into library work
Parsing module <sha512_w_mem>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/common/sync_reset.v" into library work
Parsing module <sync_reset>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" into library work
Parsing module <coretest_hashes>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v" into library work
Parsing module <bclk_dll>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/clk_dll/clk_dll.v" into library work
Parsing module <clk_dll>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/dcm_delay/dcm_delay.v" into library work
Parsing module <dcm_delay>.
Analyzing Verilog file "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" into library work
Parsing module <novena_fpga>.
=========================================================================
* HDL Elaboration *
=========================================================================
WARNING:HDLCompiler:1016 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 430: Port clk133_p90 is not connected to this instance
WARNING:HDLCompiler:1016 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 434: Port clk133_p90 is not connected to this instance
Elaborating module <novena_fpga>.
Elaborating module <sync_reset>.
Elaborating module <FDPE>.
Elaborating module <IBUFG>.
Elaborating module <BUFG>.
Elaborating module <bclk_dll>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=2,CLKFX_MULTIPLY=2,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=7.518,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="NONE",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v" Line 112: Assignment to clk0 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v" Line 128: Assignment to status_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 424: Assignment to bclk_locked ignored, since the identifier is never used
Elaborating module <dcm_delay>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=1,CLKFX_MULTIPLY=4,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=7.518,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="1X",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/dcm_delay/dcm_delay.v" Line 137: Assignment to status_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 431: Assignment to i_fbk_out ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 432: Assignment to i_locked ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 435: Assignment to o_fbk_out ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 436: Assignment to o_locked ignored, since the identifier is never used
Elaborating module <BUFIO2FB>.
Elaborating module <clk_dll>.
Elaborating module <DCM_SP(CLKDV_DIVIDE=2.0,CLKFX_DIVIDE=1,CLKFX_MULTIPLY=4,CLKIN_DIVIDE_BY_2="FALSE",CLKIN_PERIOD=20.0,CLKOUT_PHASE_SHIFT="NONE",CLK_FEEDBACK="1X",DESKEW_ADJUST="SYSTEM_SYNCHRONOUS",PHASE_SHIFT=0,STARTUP_WAIT="FALSE")>.
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/clk_dll/clk_dll.v" Line 135: Assignment to status_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 459: Assignment to dll_locked ignored, since the identifier is never used
Elaborating module <FDSE>.
WARNING:HDLCompiler:413 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" Line 490: Result of 25-bit expression is truncated to fit in 24-bit target.
Elaborating module <IBUFGDS>.
Elaborating module <IOBUF(DRIVE=12,SLEW="FAST")>.
Elaborating module <coretest_hashes>.
Elaborating module <sha1>.
Elaborating module <sha1_core>.
Elaborating module <sha1_w_mem>.
Elaborating module <sha256>.
Elaborating module <sha256_core>.
Elaborating module <sha256_k_constants>.
Elaborating module <sha256_w_mem>.
Elaborating module <sha512>.
Elaborating module <sha512_core>.
Elaborating module <sha512_k_constants>.
Elaborating module <sha512_h_constants>.
Elaborating module <sha512_w_mem>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <novena_fpga>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v".
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 423: Output port <LOCKED> of the instance <bclk_dll_mod> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <clk133_p90> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <clk133_p180> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <clk133_p270> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <CLKFB_OUT> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 430: Output port <LOCKED> of the instance <bclk_i_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <clk133_p90> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <clk133_p180> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <clk133_p270> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <CLKFB_OUT> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 434: Output port <LOCKED> of the instance <bclk_o_dll> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/novena_fpga.v" line 450: Output port <LOCKED> of the instance <clk_dll> is unconnected or connected to loadless signal.
Found 1-bit register for signal <rw_in>.
Found 16-bit register for signal <din_in>.
Found 1-bit register for signal <adv_in>.
Found 3-bit register for signal <a_in>.
Found 1-bit register for signal <cs0_r>.
Found 1-bit register for signal <rw_r>.
Found 16-bit register for signal <din_r>.
Found 1-bit register for signal <adv_r>.
Found 19-bit register for signal <bus_addr_r>.
Found 16-bit register for signal <ro_d_r>.
Found 2-bit register for signal <eim_rdcs>.
Found 16-bit register for signal <eim_dout_pipe>.
Found 16-bit register for signal <eim_dout_pipe2>.
Found 24-bit register for signal <counter>.
Found 1-bit register for signal <eim_lba_reg>.
Found 1-bit register for signal <eim_oe_reg>.
Found 16-bit register for signal <eim_d_t>.
Found 1-bit register for signal <cs0_in>.
Found 24-bit adder for signal <counter[23]_GND_1_o_add_16_OUT> created at line 490.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 152 D-type flip-flop(s).
Unit <novena_fpga> synthesized.
Synthesizing Unit <sync_reset>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/common/sync_reset.v".
Summary:
no macro.
Unit <sync_reset> synthesized.
Synthesizing Unit <bclk_dll>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/bclk_dll/bclk_dll.v".
Summary:
no macro.
Unit <bclk_dll> synthesized.
Synthesizing Unit <dcm_delay>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/dcm_delay/dcm_delay.v".
Summary:
no macro.
Unit <dcm_delay> synthesized.
Synthesizing Unit <clk_dll>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/ip/clk_dll/clk_dll.v".
Summary:
no macro.
Unit <clk_dll> synthesized.
Synthesizing Unit <coretest_hashes>.
Related source file is "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v".
SHA1_ADDR_PREFIX = 7'b1000010
SHA256_ADDR_PREFIX = 7'b1000011
SHA512_ADDR_PREFIX = 7'b1000100
WARNING:Xst:647 - Input <address<11:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" line 108: Output port <error> of the instance <sha1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" line 125: Output port <error> of the instance <sha256> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/pselkirk/coretest/core/novena_eim/src/rtl/coretest_hashes.v" line 142: Output port <error> of the instance <sha512> is unconnected or connected to loadless signal.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Found 1-bit tristate buffer for signal <read_data<15>> created at line 164
Found 1-bit tristate buffer for signal <read_data<14>> created at line 164
Found 1-bit tristate buffer for signal <read_data<13>> created at line 164
Found 1-bit tristate buffer for signal <read_data<12>> created at line 164
Found 1-bit tristate buffer for signal <read_data<11>> created at line 164
Found 1-bit tristate buffer for signal <read_data<10>> created at line 164
Found 1-bit tristate buffer for signal <read_data<9>> created at line 164
Found 1-bit tristate buffer for signal <read_data<8>> created at line 164
Found 1-bit tristate buffer for signal <read_data<7>> created at line 164
Found 1-bit tristate buffer for signal <read_data<6>> created at line 164
Found 1-bit tristate buffer for signal <read_data<5>> created at line 164
Found 1-bit tristate buffer for signal <read_data<4>> created at line 164
Found 1-bit tristate buffer for signal <read_data<3>> created at line 164
Found 1-bit tristate buffer for signal <read_data<2>> created at line 164
Found 1-bit tristate buffer for signal <read_data<1>> created at line 164
Found 1-bit tristate buffer for signal <read_data<0>> created at line 164
WARNING:Xst:737 - Found 1-bit latch for signal <write_reg<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 32 Latch(s).
inferred 46 Multiplexer(s).
inferred 16 Tristate(s).
Unit <coretest_hashes> synthesized.
Synthesizing Unit <sha1>.
Related source file is "/home/pselkirk/coretest/core/sha1/src/rtl/sha1.v".
ADDR_NAME0 = 8'b00000000
ADDR_NAME1 = 8'b00000001
ADDR_VERSION = 8'b00000010
ADDR_CTRL = 8'b00001000
CTRL_INIT_BIT = 0
CTRL_NEXT_BIT = 1
ADDR_STATUS = 8'b00001001
STATUS_READY_BIT = 0
STATUS_VALID_BIT = 1
ADDR_BLOCK0 = 8'b00010000
ADDR_BLOCK1 = 8'b00010001
ADDR_BLOCK2 = 8'b00010010
ADDR_BLOCK3 = 8'b00010011
ADDR_BLOCK4 = 8'b00010100
ADDR_BLOCK5 = 8'b00010101
ADDR_BLOCK6 = 8'b00010110
ADDR_BLOCK7 = 8'b00010111
ADDR_BLOCK8 = 8'b00011000
ADDR_BLOCK9 = 8'b00011001
ADDR_BLOCK10 = 8'b00011010
ADDR_BLOCK11 = 8'b00011011
ADDR_BLOCK12 = 8'b00011100
ADDR_BLOCK13 = 8'b00011101
ADDR_BLOCK14 = 8'b00011110
ADDR_BLOCK15 = 8'b00011111
ADDR_DIGEST0 = 8'b00100000
ADDR_DIGEST1 = 8'b00100001
ADDR_DIGEST2 = 8'b00100010
ADDR_DIGEST3 = 8'b00100011
ADDR_DIGEST4 = 8'b00100100
CORE_NAME0 = 32'b01110011011010000110000100110001
CORE_NAME1 = 32'b00100000001000000010000000100000
CORE_VERSION = 32'b00110000001011100011010100110000
Found 1-bit register for signal <next_reg>.
Found 1-bit register for signal <ready_reg>.
Found 160-bit register for signal <digest_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 32-bit register for signal <block0_reg>.
Found 32-bit register for signal <block1_reg>.
Found 32-bit register for signal <block2_reg>.
Found 32-bit register for signal <block3_reg>.
Found 32-bit register for signal <block4_reg>.
Found 32-bit register for signal <block5_reg>.
Found 32-bit register for signal <block6_reg>.
Found 32-bit register for signal <block7_reg>.
Found 32-bit register for signal <block8_reg>.
Found 32-bit register for signal <block9_reg>.
Found 32-bit register for signal <block10_reg>.
Found 32-bit register for signal <block11_reg>.
Found 32-bit register for signal <block12_reg>.
Found 32-bit register for signal <block13_reg>.
Found 32-bit register for signal <block14_reg>.
Found 32-bit register for signal <block15_reg>.
Found 1-bit register for signal <init_reg>.
Summary:
inferred 676 D-type flip-flop(s).
inferred 44 Multiplexer(s).
Unit <sha1> synthesized.
Synthesizing Unit <sha1_core>.
Related source file is "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_core.v".
H0_0 = 32'b01100111010001010010001100000001
H0_1 = 32'b11101111110011011010101110001001
H0_2 = 32'b10011000101110101101110011111110
H0_3 = 32'b00010000001100100101010001110110
H0_4 = 32'b11000011110100101110000111110000
SHA1_ROUNDS = 79
CTRL_IDLE = 0
CTRL_ROUNDS = 1
CTRL_DONE = 2
Found 32-bit register for signal <b_reg>.
Found 32-bit register for signal <c_reg>.
Found 32-bit register for signal <d_reg>.
Found 32-bit register for signal <e_reg>.
Found 32-bit register for signal <H0_reg>.
Found 32-bit register for signal <H1_reg>.
Found 32-bit register for signal <H2_reg>.
Found 32-bit register for signal <H3_reg>.
Found 32-bit register for signal <H4_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 7-bit register for signal <round_ctr_reg>.
Found 2-bit register for signal <sha1_ctrl_reg>.
Found 32-bit register for signal <a_reg>.
Found finite state machine <FSM_0> for signal <sha1_ctrl_reg>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 9 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | clk (rising_edge) |
| Reset | reset_n_INV_23_o (positive) |
| Reset type | synchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 32-bit adder for signal <H0_reg[31]_a_reg[31]_add_43_OUT> created at line 240.
Found 32-bit adder for signal <H1_reg[31]_b_reg[31]_add_44_OUT> created at line 241.
Found 32-bit adder for signal <H2_reg[31]_c_reg[31]_add_45_OUT> created at line 242.
Found 32-bit adder for signal <H3_reg[31]_d_reg[31]_add_46_OUT> created at line 243.
Found 32-bit adder for signal <H4_reg[31]_e_reg[31]_add_47_OUT> created at line 244.
Found 32-bit adder for signal <n0247> created at line 320.
Found 32-bit adder for signal <n0250> created at line 320.
Found 32-bit adder for signal <n0253> created at line 320.
Found 32-bit adder for signal <a_reg[26]_w[31]_add_93_OUT> created at line 320.
Found 7-bit adder for signal <round_ctr_reg[6]_GND_18_o_add_103_OUT> created at line 351.
Found 1-bit 4-to-1 multiplexer for signal <sha1_ctrl_we> created at line 378.
Found 7-bit comparator lessequal for signal <n0068> created at line 298
Found 7-bit comparator lessequal for signal <n0074> created at line 303
Found 7-bit comparator lessequal for signal <n0076> created at line 303
Found 7-bit comparator lessequal for signal <n0079> created at line 308
Found 7-bit comparator lessequal for signal <n0081> created at line 308
Found 7-bit comparator lessequal for signal <n0089> created at line 313
Summary:
inferred 10 Adder/Subtractor(s).
inferred 328 D-type flip-flop(s).
inferred 6 Comparator(s).
inferred 29 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <sha1_core> synthesized.
Synthesizing Unit <sha1_w_mem>.
Related source file is "/home/pselkirk/coretest/core/sha1/src/rtl/sha1_w_mem.v".
SHA1_ROUNDS = 79
CTRL_IDLE = 1'b0
CTRL_UPDATE = 1'b1
Found 7-bit register for signal <w_ctr_reg>.
Found 1-bit register for signal <sha1_w_mem_ctrl_reg>.
Found 512-bit register for signal <n0061[511:0]>.
Found 7-bit adder for signal <w_ctr_reg[6]_GND_19_o_add_52_OUT> created at line 296.
Found 32-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][31]_wide_mux_9_OUT> created at line 185.
Found 7-bit comparator greater for signal <w_ctr_reg[6]_GND_19_o_LessThan_9_o> created at line 183
Found 7-bit comparator greater for signal <GND_19_o_w_ctr_reg[6]_LessThan_15_o> created at line 254
Summary:
inferred 1 Adder/Subtractor(s).
inferred 520 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 40 Multiplexer(s).
Unit <sha1_w_mem> synthesized.
Synthesizing Unit <sha256>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256.v".
ADDR_NAME0 = 8'b00000000
ADDR_NAME1 = 8'b00000001
ADDR_VERSION = 8'b00000010
ADDR_CTRL = 8'b00001000
CTRL_INIT_BIT = 0
CTRL_NEXT_BIT = 1
ADDR_STATUS = 8'b00001001
STATUS_READY_BIT = 0
STATUS_VALID_BIT = 1
ADDR_BLOCK0 = 8'b00010000
ADDR_BLOCK1 = 8'b00010001
ADDR_BLOCK2 = 8'b00010010
ADDR_BLOCK3 = 8'b00010011
ADDR_BLOCK4 = 8'b00010100
ADDR_BLOCK5 = 8'b00010101
ADDR_BLOCK6 = 8'b00010110
ADDR_BLOCK7 = 8'b00010111
ADDR_BLOCK8 = 8'b00011000
ADDR_BLOCK9 = 8'b00011001
ADDR_BLOCK10 = 8'b00011010
ADDR_BLOCK11 = 8'b00011011
ADDR_BLOCK12 = 8'b00011100
ADDR_BLOCK13 = 8'b00011101
ADDR_BLOCK14 = 8'b00011110
ADDR_BLOCK15 = 8'b00011111
ADDR_DIGEST0 = 8'b00100000
ADDR_DIGEST1 = 8'b00100001
ADDR_DIGEST2 = 8'b00100010
ADDR_DIGEST3 = 8'b00100011
ADDR_DIGEST4 = 8'b00100100
ADDR_DIGEST5 = 8'b00100101
ADDR_DIGEST6 = 8'b00100110
ADDR_DIGEST7 = 8'b00100111
CORE_NAME0 = 32'b01110011011010000110000100110010
CORE_NAME1 = 32'b00101101001100100011010100110110
CORE_VERSION = 32'b00110000001011100011100000110000
Found 1-bit register for signal <next_reg>.
Found 1-bit register for signal <ready_reg>.
Found 256-bit register for signal <digest_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 32-bit register for signal <block0_reg>.
Found 32-bit register for signal <block1_reg>.
Found 32-bit register for signal <block2_reg>.
Found 32-bit register for signal <block3_reg>.
Found 32-bit register for signal <block4_reg>.
Found 32-bit register for signal <block5_reg>.
Found 32-bit register for signal <block6_reg>.
Found 32-bit register for signal <block7_reg>.
Found 32-bit register for signal <block8_reg>.
Found 32-bit register for signal <block9_reg>.
Found 32-bit register for signal <block10_reg>.
Found 32-bit register for signal <block11_reg>.
Found 32-bit register for signal <block12_reg>.
Found 32-bit register for signal <block13_reg>.
Found 32-bit register for signal <block14_reg>.
Found 32-bit register for signal <block15_reg>.
Found 1-bit register for signal <init_reg>.
Summary:
inferred 772 D-type flip-flop(s).
inferred 44 Multiplexer(s).
Unit <sha256> synthesized.
Synthesizing Unit <sha256_core>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_core.v".
H0_0 = 32'b01101010000010011110011001100111
H0_1 = 32'b10111011011001111010111010000101
H0_2 = 32'b00111100011011101111001101110010
H0_3 = 32'b10100101010011111111010100111010
H0_4 = 32'b01010001000011100101001001111111
H0_5 = 32'b10011011000001010110100010001100
H0_6 = 32'b00011111100000111101100110101011
H0_7 = 32'b01011011111000001100110100011001
SHA256_ROUNDS = 63
CTRL_IDLE = 0
CTRL_ROUNDS = 1
CTRL_DONE = 2
Found 32-bit register for signal <b_reg>.
Found 32-bit register for signal <c_reg>.
Found 32-bit register for signal <d_reg>.
Found 32-bit register for signal <e_reg>.
Found 32-bit register for signal <f_reg>.
Found 32-bit register for signal <g_reg>.
Found 32-bit register for signal <h_reg>.
Found 32-bit register for signal <H0_reg>.
Found 32-bit register for signal <H1_reg>.
Found 32-bit register for signal <H2_reg>.
Found 32-bit register for signal <H3_reg>.
Found 32-bit register for signal <H4_reg>.
Found 32-bit register for signal <H5_reg>.
Found 32-bit register for signal <H6_reg>.
Found 32-bit register for signal <H7_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 6-bit register for signal <t_ctr_reg>.
Found 2-bit register for signal <sha256_ctrl_reg>.
Found 32-bit register for signal <a_reg>.
Found finite state machine <FSM_1> for signal <sha256_ctrl_reg>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 9 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | clk (rising_edge) |
| Reset | reset_n_INV_63_o (positive) |
| Reset type | synchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 32-bit adder for signal <H0_reg[31]_a_reg[31]_add_64_OUT> created at line 290.
Found 32-bit adder for signal <H1_reg[31]_b_reg[31]_add_65_OUT> created at line 291.
Found 32-bit adder for signal <H2_reg[31]_c_reg[31]_add_66_OUT> created at line 292.
Found 32-bit adder for signal <H3_reg[31]_d_reg[31]_add_67_OUT> created at line 293.
Found 32-bit adder for signal <H4_reg[31]_e_reg[31]_add_68_OUT> created at line 294.
Found 32-bit adder for signal <H5_reg[31]_f_reg[31]_add_69_OUT> created at line 295.
Found 32-bit adder for signal <H6_reg[31]_g_reg[31]_add_70_OUT> created at line 296.
Found 32-bit adder for signal <H7_reg[31]_h_reg[31]_add_71_OUT> created at line 297.
Found 32-bit adder for signal <n0313> created at line 319.
Found 32-bit adder for signal <n0316> created at line 319.
Found 32-bit adder for signal <n0319> created at line 319.
Found 32-bit adder for signal <t1> created at line 319.
Found 32-bit adder for signal <t2> created at line 339.
Found 32-bit adder for signal <t1[31]_t2[31]_add_114_OUT> created at line 394.
Found 32-bit adder for signal <d_reg[31]_t1[31]_add_115_OUT> created at line 398.
Found 6-bit adder for signal <t_ctr_reg[5]_GND_21_o_add_124_OUT> created at line 426.
Found 1-bit 4-to-1 multiplexer for signal <sha256_ctrl_we> created at line 461.
Summary:
inferred 16 Adder/Subtractor(s).
inferred 519 D-type flip-flop(s).
inferred 39 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <sha256_core> synthesized.
Synthesizing Unit <sha256_k_constants>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_k_constants.v".
Found 64x32-bit Read Only RAM for signal <tmp_K>
Summary:
inferred 1 RAM(s).
Unit <sha256_k_constants> synthesized.
Synthesizing Unit <sha256_w_mem>.
Related source file is "/home/pselkirk/coretest/core/sha256/src/rtl/sha256_w_mem.v".
CTRL_IDLE = 0
CTRL_UPDATE = 1
Found 6-bit register for signal <w_ctr_reg>.
Found 2-bit register for signal <sha256_w_mem_ctrl_reg>.
Found 512-bit register for signal <n0070[511:0]>.
Found 32-bit adder for signal <n0135> created at line 233.
Found 32-bit adder for signal <n0138> created at line 233.
Found 32-bit adder for signal <w_new> created at line 233.
Found 6-bit adder for signal <w_ctr_reg[5]_GND_23_o_add_58_OUT> created at line 296.
Found 32-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][31]_wide_mux_12_OUT> created at line 178.
Found 6-bit comparator greater for signal <w_ctr_reg[5]_GND_23_o_LessThan_12_o> created at line 176
Found 6-bit comparator greater for signal <GND_23_o_w_ctr_reg[5]_LessThan_22_o> created at line 255
Summary:
inferred 4 Adder/Subtractor(s).
inferred 520 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 39 Multiplexer(s).
Unit <sha256_w_mem> synthesized.
Synthesizing Unit <sha512>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512.v".
ADDR_NAME0 = 8'b00000000
ADDR_NAME1 = 8'b00000001
ADDR_VERSION = 8'b00000010
ADDR_CTRL = 8'b00001000
CTRL_INIT_BIT = 0
CTRL_NEXT_BIT = 1
CTRL_MODE_LOW_BIT = 2
CTRL_MODE_HIGH_BIT = 3
ADDR_STATUS = 8'b00001001
STATUS_READY_BIT = 0
STATUS_VALID_BIT = 1
ADDR_BLOCK0 = 8'b00010000
ADDR_BLOCK1 = 8'b00010001
ADDR_BLOCK2 = 8'b00010010
ADDR_BLOCK3 = 8'b00010011
ADDR_BLOCK4 = 8'b00010100
ADDR_BLOCK5 = 8'b00010101
ADDR_BLOCK6 = 8'b00010110
ADDR_BLOCK7 = 8'b00010111
ADDR_BLOCK8 = 8'b00011000
ADDR_BLOCK9 = 8'b00011001
ADDR_BLOCK10 = 8'b00011010
ADDR_BLOCK11 = 8'b00011011
ADDR_BLOCK12 = 8'b00011100
ADDR_BLOCK13 = 8'b00011101
ADDR_BLOCK14 = 8'b00011110
ADDR_BLOCK15 = 8'b00011111
ADDR_BLOCK16 = 8'b00100000
ADDR_BLOCK17 = 8'b00100001
ADDR_BLOCK18 = 8'b00100010
ADDR_BLOCK19 = 8'b00100011
ADDR_BLOCK20 = 8'b00100100
ADDR_BLOCK21 = 8'b00100101
ADDR_BLOCK22 = 8'b00100110
ADDR_BLOCK23 = 8'b00100111
ADDR_BLOCK24 = 8'b00101000
ADDR_BLOCK25 = 8'b00101001
ADDR_BLOCK26 = 8'b00101010
ADDR_BLOCK27 = 8'b00101011
ADDR_BLOCK28 = 8'b00101100
ADDR_BLOCK29 = 8'b00101101
ADDR_BLOCK30 = 8'b00101110
ADDR_BLOCK31 = 8'b00101111
ADDR_DIGEST0 = 8'b01000000
ADDR_DIGEST1 = 8'b01000001
ADDR_DIGEST2 = 8'b01000010
ADDR_DIGEST3 = 8'b01000011
ADDR_DIGEST4 = 8'b01000100
ADDR_DIGEST5 = 8'b01000101
ADDR_DIGEST6 = 8'b01000110
ADDR_DIGEST7 = 8'b01000111
ADDR_DIGEST8 = 8'b01001000
ADDR_DIGEST9 = 8'b01001001
ADDR_DIGEST10 = 8'b01001010
ADDR_DIGEST11 = 8'b01001011
ADDR_DIGEST12 = 8'b01001100
ADDR_DIGEST13 = 8'b01001101
ADDR_DIGEST14 = 8'b01001110
ADDR_DIGEST15 = 8'b01001111
CORE_NAME0 = 32'b01110011011010000110000100110010
CORE_NAME1 = 32'b00101101001101010011000100110010
CORE_VERSION = 32'b00110000001011100011100000110000
MODE_SHA_512_224 = 2'b00
MODE_SHA_512_256 = 2'b01
MODE_SHA_384 = 2'b10
MODE_SHA_512 = 2'b11
Found 2-bit register for signal <mode_reg>.
Found 512-bit register for signal <digest_reg>.
Found 32-bit register for signal <block0_reg>.
Found 32-bit register for signal <block1_reg>.
Found 32-bit register for signal <block2_reg>.
Found 32-bit register for signal <block3_reg>.
Found 32-bit register for signal <block4_reg>.
Found 32-bit register for signal <block5_reg>.
Found 32-bit register for signal <block6_reg>.
Found 32-bit register for signal <block7_reg>.
Found 32-bit register for signal <block8_reg>.
Found 32-bit register for signal <block9_reg>.
Found 32-bit register for signal <block10_reg>.
Found 32-bit register for signal <block11_reg>.
Found 32-bit register for signal <block12_reg>.
Found 32-bit register for signal <block13_reg>.
Found 32-bit register for signal <block14_reg>.
Found 32-bit register for signal <block15_reg>.
Found 32-bit register for signal <block16_reg>.
Found 32-bit register for signal <block17_reg>.
Found 32-bit register for signal <block18_reg>.
Found 32-bit register for signal <block19_reg>.
Found 32-bit register for signal <block20_reg>.
Found 32-bit register for signal <block21_reg>.
Found 32-bit register for signal <block22_reg>.
Found 32-bit register for signal <block23_reg>.
Found 32-bit register for signal <block24_reg>.
Found 32-bit register for signal <block25_reg>.
Found 32-bit register for signal <block26_reg>.
Found 32-bit register for signal <block27_reg>.
Found 32-bit register for signal <block28_reg>.
Found 32-bit register for signal <block29_reg>.
Found 32-bit register for signal <block30_reg>.
Found 32-bit register for signal <block31_reg>.
Found 1-bit register for signal <next_reg>.
Found 1-bit register for signal <ready_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found 1-bit register for signal <init_reg>.
Summary:
inferred 1542 D-type flip-flop(s).
inferred 81 Multiplexer(s).
Unit <sha512> synthesized.
Synthesizing Unit <sha512_core>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_core.v".
SHA512_ROUNDS = 79
CTRL_IDLE = 0
CTRL_ROUNDS = 1
CTRL_DONE = 2
Found 64-bit register for signal <b_reg>.
Found 64-bit register for signal <c_reg>.
Found 64-bit register for signal <d_reg>.
Found 64-bit register for signal <e_reg>.
Found 64-bit register for signal <f_reg>.
Found 64-bit register for signal <g_reg>.
Found 64-bit register for signal <h_reg>.
Found 64-bit register for signal <H0_reg>.
Found 64-bit register for signal <H1_reg>.
Found 64-bit register for signal <H2_reg>.
Found 64-bit register for signal <H3_reg>.
Found 64-bit register for signal <H4_reg>.
Found 64-bit register for signal <H5_reg>.
Found 64-bit register for signal <H6_reg>.
Found 64-bit register for signal <H7_reg>.
Found 64-bit register for signal <a_reg>.
Found 7-bit register for signal <t_ctr_reg>.
Found 2-bit register for signal <sha512_ctrl_reg>.
Found 1-bit register for signal <digest_valid_reg>.
Found finite state machine <FSM_2> for signal <sha512_ctrl_reg>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 9 |
| Inputs | 4 |
| Outputs | 5 |
| Clock | clk (rising_edge) |
| Reset | reset_n (negative) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 64-bit adder for signal <H0_reg[63]_a_reg[63]_add_45_OUT> created at line 305.
Found 64-bit adder for signal <H1_reg[63]_b_reg[63]_add_46_OUT> created at line 306.
Found 64-bit adder for signal <H2_reg[63]_c_reg[63]_add_47_OUT> created at line 307.
Found 64-bit adder for signal <H3_reg[63]_d_reg[63]_add_48_OUT> created at line 308.
Found 64-bit adder for signal <H4_reg[63]_e_reg[63]_add_49_OUT> created at line 309.
Found 64-bit adder for signal <H5_reg[63]_f_reg[63]_add_50_OUT> created at line 310.
Found 64-bit adder for signal <H6_reg[63]_g_reg[63]_add_51_OUT> created at line 311.
Found 64-bit adder for signal <H7_reg[63]_h_reg[63]_add_52_OUT> created at line 312.
Found 64-bit adder for signal <n0303> created at line 334.
Found 64-bit adder for signal <n0306> created at line 334.
Found 64-bit adder for signal <n0309> created at line 334.
Found 64-bit adder for signal <t1> created at line 334.
Found 64-bit adder for signal <t2> created at line 354.
Found 64-bit adder for signal <t1[63]_t2[63]_add_95_OUT> created at line 409.
Found 64-bit adder for signal <d_reg[63]_t1[63]_add_96_OUT> created at line 413.
Found 7-bit adder for signal <t_ctr_reg[6]_GND_25_o_add_105_OUT> created at line 441.
Found 1-bit 4-to-1 multiplexer for signal <sha512_ctrl_we> created at line 476.
Summary:
inferred 16 Adder/Subtractor(s).
inferred 1032 D-type flip-flop(s).
inferred 47 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <sha512_core> synthesized.
Synthesizing Unit <sha512_k_constants>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_k_constants.v".
Found 128x64-bit Read Only RAM for signal <tmp_K>
Summary:
inferred 1 RAM(s).
Unit <sha512_k_constants> synthesized.
Synthesizing Unit <sha512_h_constants>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_h_constants.v".
Found 4x512-bit Read Only RAM for signal <_n0037>
Summary:
inferred 1 RAM(s).
Unit <sha512_h_constants> synthesized.
Synthesizing Unit <sha512_w_mem>.
Related source file is "/home/pselkirk/coretest/core/sha512/src/rtl/sha512_w_mem.v".
CTRL_IDLE = 1'b0
CTRL_UPDATE = 1'b1
Found 7-bit register for signal <w_ctr_reg>.
Found 1024-bit register for signal <n0061[1023:0]>.
Found 1-bit register for signal <sha512_w_mem_ctrl_reg>.
Found 64-bit adder for signal <n0120> created at line 234.
Found 64-bit adder for signal <n0123> created at line 234.
Found 64-bit adder for signal <w_new> created at line 234.
Found 7-bit adder for signal <w_ctr_reg[6]_GND_28_o_add_52_OUT> created at line 297.
Found 64-bit 16-to-1 multiplexer for signal <w_ctr_reg[3]_w_mem[15][63]_wide_mux_6_OUT> created at line 179.
Found 7-bit comparator greater for signal <w_ctr_reg[6]_GND_28_o_LessThan_6_o> created at line 177
Found 7-bit comparator greater for signal <GND_28_o_w_ctr_reg[6]_LessThan_16_o> created at line 256
Summary:
inferred 4 Adder/Subtractor(s).
inferred 1032 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 40 Multiplexer(s).
Unit <sha512_w_mem> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 3
128x64-bit single-port Read Only RAM : 1
4x512-bit single-port Read Only RAM : 1
64x32-bit single-port Read Only RAM : 1
# Adders/Subtractors : 52
24-bit adder : 1
32-bit adder : 27
6-bit adder : 2
64-bit adder : 18
7-bit adder : 4
# Registers : 142
1-bit register : 25
1024-bit register : 1
16-bit register : 5
160-bit register : 2
19-bit register : 2
2-bit register : 3
24-bit register : 1
256-bit register : 2
32-bit register : 75
512-bit register : 3
6-bit register : 2
64-bit register : 17
7-bit register : 4
# Latches : 32
1-bit latch : 32
# Comparators : 12
6-bit comparator greater : 2
7-bit comparator greater : 4
7-bit comparator lessequal : 6
# Multiplexers : 449
1-bit 2-to-1 multiplexer : 228
1-bit 4-to-1 multiplexer : 3
2-bit 2-to-1 multiplexer : 3
32-bit 16-to-1 multiplexer : 2
32-bit 2-to-1 multiplexer : 131
6-bit 2-to-1 multiplexer : 2
64-bit 16-to-1 multiplexer : 1
64-bit 2-to-1 multiplexer : 73
7-bit 2-to-1 multiplexer : 3
8-bit 2-to-1 multiplexer : 3
# Tristates : 16
1-bit tristate buffer : 16
# FSMs : 3
# Xors : 28
32-bit xor2 : 16
32-bit xor4 : 1
64-bit xor2 : 11
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <novena_fpga>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <novena_fpga> synthesized (advanced).
Synthesizing (advanced) Unit <sha1_core>.
The following registers are absorbed into counter <round_ctr_reg>: 1 register on signal <round_ctr_reg>.
The following adders/subtractors are grouped into adder tree <Madd_a_reg[26]_w[31]_add_93_OUT1> :
<Madd_n0247> in block <sha1_core>, <Madd_n0250> in block <sha1_core>, <Madd_n0253> in block <sha1_core>, <Madd_a_reg[26]_w[31]_add_93_OUT> in block <sha1_core>.
Unit <sha1_core> synthesized (advanced).
Synthesizing (advanced) Unit <sha1_w_mem>.
The following registers are absorbed into counter <w_ctr_reg>: 1 register on signal <w_ctr_reg>.
Unit <sha1_w_mem> synthesized (advanced).
Synthesizing (advanced) Unit <sha256_core>.
The following registers are absorbed into counter <t_ctr_reg>: 1 register on signal <t_ctr_reg>.
The following adders/subtractors are grouped into adder tree <Madd_t11> :
<Madd_n0313> in block <sha256_core>, <Madd_n0316> in block <sha256_core>, <Madd_n0319> in block <sha256_core>, <Madd_t1> in block <sha256_core>.
Unit <sha256_core> synthesized (advanced).
Synthesizing (advanced) Unit <sha256_k_constants>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_tmp_K> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 64-word x 32-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <addr> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <tmp_K> | |
-----------------------------------------------------------------------
Unit <sha256_k_constants> synthesized (advanced).
Synthesizing (advanced) Unit <sha256_w_mem>.
The following registers are absorbed into counter <w_ctr_reg>: 1 register on signal <w_ctr_reg>.
The following adders/subtractors are grouped into adder tree <Madd_w_new1> :
<Madd_n0135> in block <sha256_w_mem>, <Madd_n0138> in block <sha256_w_mem>, <Madd_w_new> in block <sha256_w_mem>.
Unit <sha256_w_mem> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_core>.
The following registers are absorbed into accumulator <H1_reg>: 1 register on signal <H1_reg>.
The following registers are absorbed into accumulator <H3_reg>: 1 register on signal <H3_reg>.
The following registers are absorbed into accumulator <H2_reg>: 1 register on signal <H2_reg>.
The following registers are absorbed into accumulator <H5_reg>: 1 register on signal <H5_reg>.
The following registers are absorbed into accumulator <H4_reg>: 1 register on signal <H4_reg>.
The following registers are absorbed into accumulator <H6_reg>: 1 register on signal <H6_reg>.
The following registers are absorbed into accumulator <H7_reg>: 1 register on signal <H7_reg>.
The following registers are absorbed into accumulator <H0_reg>: 1 register on signal <H0_reg>.
The following registers are absorbed into counter <t_ctr_reg>: 1 register on signal <t_ctr_reg>.
Unit <sha512_core> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_h_constants>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0037> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 4-word x 512-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <mode> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <sha512_h_constants> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_k_constants>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_tmp_K> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 128-word x 64-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <addr> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <tmp_K> | |
-----------------------------------------------------------------------
Unit <sha512_k_constants> synthesized (advanced).
Synthesizing (advanced) Unit <sha512_w_mem>.
The following registers are absorbed into counter <w_ctr_reg>: 1 register on signal <w_ctr_reg>.
Unit <sha512_w_mem> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 3
128x64-bit single-port distributed Read Only RAM : 1
4x512-bit single-port distributed Read Only RAM : 1
64x32-bit single-port distributed Read Only RAM : 1
# Adders/Subtractors : 26
32-bit adder : 16
64-bit adder : 10
# Adder Trees : 3
32-bit / 4-inputs adder tree : 1
32-bit / 5-inputs adder tree : 2
# Counters : 7
24-bit up counter : 1
6-bit up counter : 2
7-bit up counter : 4
# Accumulators : 8
64-bit up loadable accumulator : 8
# Registers : 6537
Flip-Flops : 6537
# Comparators : 12
6-bit comparator greater : 2
7-bit comparator greater : 4
7-bit comparator lessequal : 6
# Multiplexers : 592
1-bit 16-to-1 multiplexer : 128
1-bit 2-to-1 multiplexer : 260
1-bit 4-to-1 multiplexer : 3
2-bit 2-to-1 multiplexer : 3
32-bit 2-to-1 multiplexer : 130
64-bit 2-to-1 multiplexer : 65
8-bit 2-to-1 multiplexer : 3
# FSMs : 3
# Xors : 28
32-bit xor2 : 16
32-bit xor4 : 1
64-bit xor2 : 11
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <sha256_w_mem_ctrl_reg_1> (without init value) has a constant value of 0 in block <sha256_w_mem>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <eim_d_t_0> in Unit <novena_fpga> is equivalent to the following 15 FFs/Latches, which will be removed : <eim_d_t_1> <eim_d_t_2> <eim_d_t_3> <eim_d_t_4> <eim_d_t_5> <eim_d_t_6> <eim_d_t_7> <eim_d_t_8> <eim_d_t_9> <eim_d_t_10> <eim_d_t_11> <eim_d_t_12> <eim_d_t_13> <eim_d_t_14> <eim_d_t_15>
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <core/sha1/core/FSM_0> on signal <sha1_ctrl_reg[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <core/sha256/core/FSM_1> on signal <sha256_ctrl_reg[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <core/sha512/core/FSM_2> on signal <sha512_ctrl_reg[1:2]> with user encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 10
-------------------
WARNING:Xst:2042 - Unit coretest_hashes: 16 internal tristates are replaced by logic (pull-up yes): read_data<0>, read_data<10>, read_data<11>, read_data<12>, read_data<13>, read_data<14>, read_data<15>, read_data<1>, read_data<2>, read_data<3>, read_data<4>, read_data<5>, read_data<6>, read_data<7>, read_data<8>, read_data<9>.
Optimizing unit <novena_fpga> ...
Optimizing unit <coretest_hashes> ...
Optimizing unit <sha1> ...
Optimizing unit <sha1_core> ...
Optimizing unit <sha1_w_mem> ...
Optimizing unit <sha256> ...
Optimizing unit <sha256_core> ...
Optimizing unit <sha256_w_mem> ...
Optimizing unit <sha512> ...
Optimizing unit <sha512_core> ...
Optimizing unit <sha512_w_mem> ...
WARNING:Xst:2677 - Node <bus_addr_r_10> of sequential type is unconnected in block <novena_fpga>.
WARNING:Xst:2677 - Node <bus_addr_r_11> of sequential type is unconnected in block <novena_fpga>.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block novena_fpga, actual ratio is 50.
FlipFlop bus_addr_r_12 has been replicated 1 time(s)
FlipFlop bus_addr_r_2 has been replicated 1 time(s)
FlipFlop bus_addr_r_3 has been replicated 1 time(s)
FlipFlop bus_addr_r_4 has been replicated 1 time(s)
FlipFlop core/sha1/init_reg has been replicated 1 time(s)
FlipFlop core/sha1/next_reg has been replicated 1 time(s)
FlipFlop core/sha256/core/sha256_ctrl_reg_FSM_FFd1 has been replicated 1 time(s)
FlipFlop core/sha256/init_reg has been replicated 1 time(s)
FlipFlop core/sha256/next_reg has been replicated 1 time(s)
FlipFlop core/sha512/core/digest_valid_reg has been replicated 1 time(s)
FlipFlop core/sha512/core/sha512_ctrl_reg_FSM_FFd1 has been replicated 2 time(s)
FlipFlop core/sha512/core/sha512_ctrl_reg_FSM_FFd2 has been replicated 1 time(s)
FlipFlop core/sha512/init_reg has been replicated 2 time(s)
FlipFlop core/sha512/next_reg has been replicated 2 time(s)
Final Macro Processing ...
Processing Unit <novena_fpga> :
Found 2-bit shift register for signal <din_r_10>.
Found 2-bit shift register for signal <din_r_11>.
Found 2-bit shift register for signal <rw_r>.
Found 2-bit shift register for signal <cs0_r>.
Unit <novena_fpga> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 7110
Flip-Flops : 7110
# Shift Registers : 4
2-bit shift register : 4
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : novena_eim.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 13371
# BUF : 13
# GND : 1
# INV : 3
# LUT1 : 23
# LUT2 : 1346
# LUT3 : 1015
# LUT4 : 908
# LUT5 : 698
# LUT6 : 5765
# MUXCY : 1556
# MUXF7 : 322
# MUXF8 : 128
# VCC : 1
# XORCY : 1592
# FlipFlops/Latches : 7146
# FD : 102
# FDC : 16
# FDCE : 3598
# FDE : 25
# FDP : 4
# FDPE : 2
# FDR : 36
# FDRE : 3315
# FDSE : 16
# LDE : 16
# LDE_1 : 16
# Shift Registers : 4
# SRLC16E : 4
# Clock Buffers : 14
# BUFG : 14
# IO Buffers : 29
# IBUF : 9
# IBUFG : 1
# IBUFGDS : 1
# IOBUF : 16
# OBUF : 2
# DCMs : 4
# DCM_SP : 4
# Others : 1
# BUFIO2FB : 1
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-3
Slice Logic Utilization:
Number of Slice Registers: 7146 out of 54576 13%
Number of Slice LUTs: 9762 out of 27288 35%
Number used as Logic: 9758 out of 27288 35%
Number used as Memory: 4 out of 6408 0%
Number used as SRL: 4
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 12258
Number with an unused Flip Flop: 5112 out of 12258 41%
Number with an unused LUT: 2496 out of 12258 20%
Number of fully used LUT-FF pairs: 4650 out of 12258 37%
Number of unique control sets: 123
IO Utilization:
Number of IOs: 30
Number of bonded IOBs: 30 out of 218 13%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 14 out of 16 87%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-------------------------------------------------------------+---------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-------------------------------------------------------------+---------------------------+-------+
EIM_BCLK | DCM_SP:CLKFX | 131 |
CLK2_P | DCM_SP:CLK0 | 24 |
core/cs_we_AND_247_o(core/cs_we_AND_247_o1:O) | NONE(*)(core/write_reg_16)| 16 |
core/cs_address[1]_AND_248_o(core/cs_address[1]_AND_248_o1:O)| NONE(*)(core/write_reg_0) | 16 |
CLK2_P | DCM_SP:CLKDV | 6959 |
CLK2_P | DCM_SP:CLK2X | 4 |
-------------------------------------------------------------+---------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 10.512ns (Maximum Frequency: 95.125MHz)
Minimum input arrival time before clock: 3.119ns
Maximum output required time after clock: 4.022ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'EIM_BCLK'
Clock period: 9.819ns (frequency: 101.846MHz)
Total number of paths / destination ports: 52122 / 142
-------------------------------------------------------------------------
Delay: 9.819ns (Levels of Logic = 7)
Source: bus_addr_r_15 (FF)
Destination: ro_d_r_8 (FF)
Source Clock: EIM_BCLK rising
Destination Clock: EIM_BCLK rising
Data Path: bus_addr_r_15 to ro_d_r_8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 19 0.447 1.416 bus_addr_r_15 (bus_addr_r_15)
LUT6:I1->O 363 0.203 2.077 core/address[18]_PWR_16_o_equal_4_o<18>21 (core/address[18]_PWR_16_o_equal_4_o<18>2)
LUT6:I5->O 33 0.205 1.534 core/sha1/address[7]_GND_17_o_equal_107_o<7>1 (core/sha1/address[7]_GND_17_o_equal_107_o)
LUT6:I3->O 1 0.205 0.827 core/read_data<8>LogicTrst75 (core/read_data<8>LogicTrst74)
LUT6:I2->O 1 0.203 0.580 core/read_data<8>LogicTrst84_SW0 (N71)
LUT6:I5->O 1 0.205 0.827 core/read_data<8>LogicTrst84 (core/read_data<8>LogicTrst83)
LUT5:I1->O 1 0.203 0.580 core/read_data<8>LogicTrst96_SW0 (N360)
LUT6:I5->O 1 0.205 0.000 core/read_data<8>LogicTrst96 (ro_d<8>)
FD:D 0.102 ro_d_r_8
----------------------------------------
Total 9.819ns (1.978ns logic, 7.841ns route)
(20.1% logic, 79.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK2_P'
Clock period: 10.512ns (frequency: 95.125MHz)
Total number of paths / destination ports: 3205234486 / 16738
-------------------------------------------------------------------------
Delay: 5.256ns (Levels of Logic = 1)
Source: dll_res_sync/fdres3 (FF)
Destination: core/sha1/digest_reg_159 (FF)
Source Clock: CLK2_P rising 2.0X
Destination Clock: CLK2_P rising 0.5X
Data Path: dll_res_sync/fdres3 to core/sha1/digest_reg_159
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDP:C->Q 497 0.447 2.087 dll_res_sync/fdres3 (core/sha1/core/Reset_OR_DriverANDClockEnable)
BUF:I->O 497 0.206 2.087 dll_res_sync/fdres3_1 (dll_res_sync/fdres3_1)
FDC:CLR 0.430 core/sha512/next_reg_2
----------------------------------------
Total 5.256ns (1.083ns logic, 4.173ns route)
(20.6% logic, 79.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'EIM_BCLK'
Total number of paths / destination ports: 26 / 26
-------------------------------------------------------------------------
Offset: 2.725ns (Levels of Logic = 2)
Source: EIM_LBA (PAD)
Destination: adv_in (FF)
Destination Clock: EIM_BCLK rising
Data Path: EIM_LBA to adv_in
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.222 0.616 EIM_LBA_IBUF (EIM_LBA_IBUF)
INV:I->O 1 0.206 0.579 adv_in_rstpot1_INV_0 (adv_in_rstpot)
FD:D 0.102 adv_in
----------------------------------------
Total 2.725ns (1.530ns logic, 1.195ns route)
(56.1% logic, 43.9% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK2_P'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 3.119ns (Levels of Logic = 2)
Source: RESETBMCU (PAD)
Destination: dll_res_sync/fdres3 (FF)
Destination Clock: CLK2_P rising 2.0X
Data Path: RESETBMCU to dll_res_sync/fdres3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.222 0.579 RESETBMCU_IBUF (RESETBMCU_IBUF)
INV:I->O 4 0.206 0.683 RESETBMCU_INV_3_o1_INV_0 (RESETBMCU_INV_3_o)
FDP:PRE 0.430 dll_res_sync/fdres3
----------------------------------------
Total 3.119ns (1.858ns logic, 1.261ns route)
(59.6% logic, 40.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'EIM_BCLK'
Total number of paths / destination ports: 32 / 16
-------------------------------------------------------------------------
Offset: 4.022ns (Levels of Logic = 1)
Source: eim_d_t_0 (FF)
Destination: EIM_DA<15> (PAD)
Source Clock: EIM_BCLK rising
Data Path: eim_d_t_0 to EIM_DA<15>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 16 0.447 1.004 eim_d_t_0 (eim_d_t_0)
IOBUF:T->IO 2.571 IOBUF_eim0 (EIM_DA<0>)
----------------------------------------
Total 4.022ns (3.018ns logic, 1.004ns route)
(75.0% logic, 25.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK2_P'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 3.634ns (Levels of Logic = 1)
Source: counter_23 (FF)
Destination: FPGA_LED2 (PAD)
Source Clock: CLK2_P rising
Data Path: counter_23 to FPGA_LED2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.447 0.616 counter_23 (counter_23)
OBUF:I->O 2.571 FPGA_LED2_OBUF (FPGA_LED2)
----------------------------------------
Total 3.634ns (3.018ns logic, 0.616ns route)
(83.0% logic, 17.0% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock CLK2_P
----------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
CLK2_P | 12.055| | | |
EIM_BCLK | 8.814| | | |
core/cs_address[1]_AND_248_o| 3.555| | | |
core/cs_we_AND_247_o | | 1.798| | |
----------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock EIM_BCLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK2_P | 6.973| | | |
EIM_BCLK | 9.819| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock core/cs_address[1]_AND_248_o
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
EIM_BCLK | 4.523| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock core/cs_we_AND_247_o
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
EIM_BCLK | | | 3.786| |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 61.00 secs
Total CPU time to Xst completion: 60.00 secs
-->
Total memory usage is 477212 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 50 ( 0 filtered)
Number of infos : 20 ( 0 filtered)
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; ngdbuild novena_eim.ngc -bm novena_eim.bmm
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - ngdbuild P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.3/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
novena_eim.ngc -bm novena_eim.bmm
Reading NGO file "/home/pselkirk/coretest/core/novena_eim/build/novena_eim.ngc"
...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "novena_eim.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'clk_tnm', used in period specification
'TS_clk', was traced into DCM_SP instance clk_dll/dcm_sp_inst. The following
new TNM groups and period specifications were generated at the DCM_SP
output(s):
CLK2X: <TIMESPEC TS_clk_dll_clk2x = PERIOD "clk_dll_clk2x" TS_clk * 2 HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'clk_tnm', used in period specification
'TS_clk', was traced into DCM_SP instance clk_dll/dcm_sp_inst. The following
new TNM groups and period specifications were generated at the DCM_SP
output(s):
CLK0: <TIMESPEC TS_clk_dll_clk0 = PERIOD "clk_dll_clk0" TS_clk HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'clk_tnm', used in period specification
'TS_clk', was traced into DCM_SP instance clk_dll/dcm_sp_inst. The following
new TNM groups and period specifications were generated at the DCM_SP
output(s):
CLKDV: <TIMESPEC TS_clk_dll_clkdv = PERIOD "clk_dll_clkdv" TS_clk / 2 HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'bclk_tnm', used in period specification
'TS_bclk', was traced into DCM_SP instance bclk_dll_mod/dcm_sp_inst. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLKFX: <TIMESPEC TS_bclk_dll_mod_clkfx = PERIOD "bclk_dll_mod_clkfx" TS_bclk
HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'bclk_tnm', used in period specification
'TS_bclk', was traced into DCM_SP instance bclk_o_dll/dcm_sp_inst. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK0: <TIMESPEC TS_bclk_o_dll_clk0 = PERIOD "bclk_o_dll_clk0" TS_bclk HIGH
50%>
INFO:ConstraintSystem:178 - TNM 'bclk_tnm', used in period specification
'TS_bclk', was traced into DCM_SP instance bclk_i_dll/dcm_sp_inst. The
following new TNM groups and period specifications were generated at the
DCM_SP output(s):
CLK0: <TIMESPEC TS_bclk_i_dll_clk0 = PERIOD "bclk_i_dll_clk0" TS_bclk HIGH
50%>
INFO:ConstraintSystem - The Period constraint <NET "CLK2_P" PERIOD = 20 ns;>
[novena_eim.ucf(653)], is specified using the Net Period method which is not
recommended. Please use the Timespec PERIOD method.
Done...
Processing BMM file "novena_eim.bmm" ...
WARNING::53 - File 'novena_eim.bmm' is empty or has no BMM content.
WARNING:NgdBuild:1212 - User specified non-default attribute value (7.518000)
was detected for the CLKIN_PERIOD attribute on DCM
"bclk_dll_mod/dcm_sp_inst". This does not match the PERIOD constraint value
(133 MHz.). The uncertainty calculation will use the non-default attribute
value. This could result in incorrect uncertainty calculated for DCM output
clocks.
WARNING:NgdBuild:1212 - User specified non-default attribute value (7.518000)
was detected for the CLKIN_PERIOD attribute on DCM "bclk_o_dll/dcm_sp_inst".
This does not match the PERIOD constraint value (133 MHz.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
WARNING:NgdBuild:1212 - User specified non-default attribute value (7.518000)
was detected for the CLKIN_PERIOD attribute on DCM "bclk_i_dll/dcm_sp_inst".
This does not match the PERIOD constraint value (133 MHz.). The uncertainty
calculation will use the non-default attribute value. This could result in
incorrect uncertainty calculated for DCM output clocks.
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 3
Writing NGD file "novena_eim.ngd" ...
Total REAL time to NGDBUILD completion: 8 sec
Total CPU time to NGDBUILD completion: 8 sec
Writing NGDBUILD log file "novena_eim.bld"...
NGDBUILD done.
if [ -r novena_eim_par.ncd ]; then \
cp novena_eim_par.ncd smartguide.ncd; \
smartguide="-smartguide smartguide.ncd"; \
else \
smartguide=""; \
fi; \
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
map -timing -ol high -detail -pr b -register_duplication -w $smartguide novena_eim.ngd
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - Map P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Using target part "6slx45csg324-3".
Mapping design into LUTs...
Writing file novena_eim.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3402 - The Clock Modifying COMP, bclk_dll_mod/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
FROM/TO constraints.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 25 secs
Total CPU time at the beginning of Placer: 25 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:ebe12bad) REAL time: 28 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:ebe12bad) REAL time: 29 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:ebe12bad) REAL time: 29 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:e9f2ed0c) REAL time: 49 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:e9f2ed0c) REAL time: 49 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:e9f2ed0c) REAL time: 49 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:e9f2ed0c) REAL time: 49 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:e9f2ed0c) REAL time: 49 secs
Phase 9.8 Global Placement
...........................................................................................................................
..........................................................................................................................................................................................................
................................................................................................................................................................................................................................
...............................................................................................................................
Phase 9.8 Global Placement (Checksum:5ec64119) REAL time: 2 mins 29 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:5ec64119) REAL time: 2 mins 29 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:35d56b5b) REAL time: 3 mins 43 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:35d56b5b) REAL time: 3 mins 44 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:cc990990) REAL time: 3 mins 44 secs
Total REAL time to Placer completion: 3 mins 55 secs
Total CPU time to Placer completion: 3 mins 54 secs
Running physical synthesis...
Physical synthesis completed.
Running post-placement packing...
Writing output files...
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_i_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_o_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found NO extern
Design Summary:
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 7,529 out of 54,576 13%
Number used as Flip Flops: 7,077
Number used as Latches: 32
Number used as Latch-thrus: 0
Number used as AND/OR logics: 420
Number of Slice LUTs: 8,943 out of 27,288 32%
Number used as logic: 8,779 out of 27,288 32%
Number using O6 output only: 7,778
Number using O5 output only: 22
Number using O5 and O6: 979
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 160
Number with same-slice register load: 159
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,008 out of 6,822 44%
Nummber of MUXCYs used: 1,592 out of 13,644 11%
Number of LUT Flip Flop pairs used: 10,592
Number with an unused Flip Flop: 3,441 out of 10,592 32%
Number with an unused LUT: 1,649 out of 10,592 15%
Number of fully used LUT-FF pairs: 5,502 out of 10,592 51%
Number of unique control sets: 121
Number of slice register sites lost
to control set restrictions: 199 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 30 out of 218 13%
Number of LOCed IOBs: 30 out of 30 100%
IOB Flip Flops: 37
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 8 out of 16 50%
Number used as BUFGs: 8
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 4 out of 8 50%
Number used as DCMs: 4
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 21 out of 376 5%
Number used as ILOGIC2s: 21
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 16 out of 376 4%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 5.03
Peak Memory Usage: 984 MB
Total REAL time to MAP completion: 4 mins 6 secs
Total CPU time to MAP completion: 4 mins 6 secs
Mapping completed.
See MAP report file "novena_eim.mrp" for details.
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
if par -ol high -w novena_eim.ncd novena_eim_par.ncd; then \
:; \
else \
make etwr; \
fi
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - par P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Constraints file: novena_eim.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment /opt/Xilinx/14.3/ISE_DS/ISE/.
"novena_fpga" is an NCD, version 3.2, device xc6slx45, package csg324, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2012-10-12".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 7,529 out of 54,576 13%
Number used as Flip Flops: 7,077
Number used as Latches: 32
Number used as Latch-thrus: 0
Number used as AND/OR logics: 420
Number of Slice LUTs: 8,943 out of 27,288 32%
Number used as logic: 8,779 out of 27,288 32%
Number using O6 output only: 7,778
Number using O5 output only: 22
Number using O5 and O6: 979
Number used as ROM: 0
Number used as Memory: 4 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 160
Number with same-slice register load: 159
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,008 out of 6,822 44%
Nummber of MUXCYs used: 1,592 out of 13,644 11%
Number of LUT Flip Flop pairs used: 10,592
Number with an unused Flip Flop: 3,441 out of 10,592 32%
Number with an unused LUT: 1,649 out of 10,592 15%
Number of fully used LUT-FF pairs: 5,502 out of 10,592 51%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 30 out of 218 13%
Number of LOCed IOBs: 30 out of 30 100%
IOB Flip Flops: 37
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 8 out of 16 50%
Number used as BUFGs: 8
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 4 out of 8 50%
Number used as DCMs: 4
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 21 out of 376 5%
Number used as ILOGIC2s: 21
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 16 out of 376 4%
Number used as OLOGIC2s: 16
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
WARNING:Timing:3402 - The Clock Modifying COMP, bclk_dll_mod/dcm_sp_inst, has the attribute CLK_FEEDBACK set to NONE. No phase relationship
exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
FROM/TO constraints.
Starting initial Timing Analysis. REAL time: 13 secs
Finished initial Timing Analysis. REAL time: 14 secs
Starting Router
Phase 1 : 56874 unrouted; REAL time: 15 secs
Phase 2 : 53754 unrouted; REAL time: 18 secs
Phase 3 : 31834 unrouted; REAL time: 1 mins
Phase 4 : 31834 unrouted; (Setup:10784, Hold:86173, Component Switching Limit:0) REAL time: 1 mins 5 secs
Updating file: novena_eim_par.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:10784, Hold:75450, Component Switching Limit:0) REAL time: 3 mins 46 secs
Phase 6 : 0 unrouted; (Setup:10784, Hold:75450, Component Switching Limit:0) REAL time: 3 mins 48 secs
Phase 7 : 0 unrouted; (Setup:10784, Hold:75450, Component Switching Limit:0) REAL time: 3 mins 56 secs
Phase 8 : 0 unrouted; (Setup:10784, Hold:75450, Component Switching Limit:0) REAL time: 3 mins 56 secs
WARNING:Route:522 - Unusually high hold time violation detected among 3 connections.The router will continue and try to fix it
EIM_CS<1>:I -> eim_rdcs<1>:D -4232
EIM_CS<0>:I -> EIM_CS_0_IBUF:D -4126
bus_addr_r<12>:CQ -> ro_d_r<9>:C1 -2059
Phase 9 : 0 unrouted; (Setup:10784, Hold:33210, Component Switching Limit:0) REAL time: 11 mins 5 secs
Phase 10 : 0 unrouted; (Setup:10784, Hold:33210, Component Switching Limit:0) REAL time: 11 mins 9 secs
Total REAL time to Router completion: 11 mins 9 secs
Total CPU time to Router completion: 11 mins 15 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk25 | BUFGMUX_X2Y4| No | 1706 | 0.063 | 1.276 |
+---------------------+--------------+------+------+------------+-------------+
| bclk_dll | BUFGMUX_X2Y10| No | 19 | 0.504 | 1.717 |
+---------------------+--------------+------+------+------------+-------------+
| bclk_i | BUFGMUX_X2Y12| No | 41 | 0.526 | 1.739 |
+---------------------+--------------+------+------+------------+-------------+
| bclk_o | BUFGMUX_X2Y3| No | 21 | 0.515 | 1.735 |
+---------------------+--------------+------+------+------------+-------------+
| clk50 | BUFGMUX_X2Y1| No | 7 | 0.030 | 1.251 |
+---------------------+--------------+------+------+------------+-------------+
| slowclk | BUFGMUX_X3Y13| No | 1 | 0.000 | 1.263 |
+---------------------+--------------+------+------+------------+-------------+
|core/cs_address[1]_A | | | | | |
| ND_248_o | Local| | 70 | 1.028 | 1.582 |
+---------------------+--------------+------+------+------------+-------------+
|core/cs_we_AND_247_o | | | | | |
| | Local| | 4 | 0.693 | 1.216 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 43994 (Setup: 10784, Hold: 33210, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 6
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* OFFSET = IN 4.125 ns VALID 4.75 ns BEFORE | SETUP | 1.595ns| 2.530ns| 0| 0
COMP "EIM_BCLK" | HOLD | -4.232ns| | 21| 33210
----------------------------------------------------------------------------------------------------------
* OFFSET = OUT 5.1 ns AFTER COMP "EIM_BCLK" | MAXDELAY | -0.715ns| 5.815ns| 16| 10784
----------------------------------------------------------------------------------------------------------
TS_bclk_dll_mod_clkfx = PERIOD TIMEGRP "b | SETUP | 0.015ns| 7.503ns| 0| 0
clk_dll_mod_clkfx" TS_bclk HIGH 50% | HOLD | 0.002ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_bclk_o_dll_clk0 = PERIOD TIMEGRP "bclk | SETUP | 0.369ns| 7.149ns| 0| 0
_o_dll_clk0" TS_bclk HIGH 50% | HOLD | 1.020ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_bclk_i_dll_clk0 = PERIOD TIMEGRP "bclk | SETUP | 0.614ns| 6.904ns| 0| 0
_i_dll_clk0" TS_bclk HIGH 50% | HOLD | 1.128ns| | 0| 0
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "clk_dll/clkdv" d | SETUP | 1.761ns| 32.956ns| 0| 0
erived from NET "clk" PERIOD = 20 ns HIG | HOLD | 0.370ns| | 0| 0
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_bclk = PERIOD TIMEGRP "bclk_tnm" 133 M | MINLOWPULSE | 2.178ns| 5.340ns| 0| 0
Hz HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "clk_dll/clk2x" d | SETUP | 8.384ns| 1.616ns| 0| 0
erived from NET "clk" PERIOD = 20 ns HIG | HOLD | 0.471ns| | 0| 0
H 50% | MINPERIOD | 7.330ns| 2.670ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk_tnm" 50 MHz | MINLOWPULSE | 12.000ns| 8.000ns| 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_dll_clk2x = PERIOD TIMEGRP "clk_dl | MINPERIOD | 8.270ns| 1.730ns| 0| 0
l_clk2x" TS_clk * 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
NET "clk" PERIOD = 20 ns HIGH 50% | MINLOWPULSE | 12.000ns| 8.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
PERIOD analysis for net "clk_dll/clk0" de | SETUP | 17.487ns| 2.513ns| 0| 0
rived from NET "clk" PERIOD = 20 ns HIGH | HOLD | 0.519ns| | 0| 0
50% | MINPERIOD | 16.430ns| 3.570ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_dll_clk0 = PERIOD TIMEGRP "clk_dll | MINPERIOD | 18.270ns| 1.730ns| 0| 0
_clk0" TS_clk HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_dll_clkdv = PERIOD TIMEGRP "clk_dl | MINPERIOD | 38.270ns| 1.730ns| 0| 0
l_clkdv" TS_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|clk | 20.000ns| 8.000ns| 16.478ns| 0| 0| 0| 3205234486|
| clk_dll/clk0 | 20.000ns| 3.570ns| N/A| 0| 0| 300| 0|
| clk_dll/clk2x | 10.000ns| 2.670ns| N/A| 0| 0| 3| 0|
| clk_dll/clkdv | 40.000ns| 32.956ns| N/A| 0| 0| 3205234183| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk | 20.000ns| 8.000ns| 3.460ns| 0| 0| 0| 0|
| TS_clk_dll_clk2x | 10.000ns| 1.730ns| N/A| 0| 0| 0| 0|
| TS_clk_dll_clk0 | 20.000ns| 1.730ns| N/A| 0| 0| 0| 0|
| TS_clk_dll_clkdv | 40.000ns| 1.730ns| N/A| 0| 0| 0| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_bclk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_bclk | 7.519ns| 5.340ns| 7.503ns| 0| 0| 0| 52118|
| TS_bclk_dll_mod_clkfx | 7.519ns| 7.503ns| N/A| 0| 0| 52027| 0|
| TS_bclk_o_dll_clk0 | 7.519ns| 7.149ns| N/A| 0| 0| 34| 0|
| TS_bclk_i_dll_clk0 | 7.519ns| 6.904ns| N/A| 0| 0| 57| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
2 constraints not met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 11 mins 14 secs
Total CPU time to PAR completion: 11 mins 20 secs
Peak Memory Usage: 932 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 37 errors found.
Number of error messages: 0
Number of warning messages: 3
Number of info messages: 0
Writing design to file novena_eim_par.ncd
PAR done!
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
bitgen -g UnusedPin:Pullnone -g DriveDone:yes -g StartupClk:Cclk -w novena_eim_par.ncd novena_eim.bit
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - Bitgen P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45.nph' in environment
/opt/Xilinx/14.3/ISE_DS/ISE/.
"novena_fpga" is an NCD, version 3.2, device xc6slx45, package csg324, speed
-3
Thu Nov 6 14:51:34 2014
Running DRC.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_dll_mod/dcm_sp_inst> found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_i_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_i_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<clk_dll/dcm_sp_inst>
found NO extern
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for
block<bclk_o_dll/dcm_sp_inst>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
and DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found non-EXTERN block <BUFG> in CLKIN path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<bclk_o_dll/dcm_sp_inst>
found NO extern
WARNING:PhysDesignRules:372 - Gated clock. Clock net
core/cs_address[1]_AND_248_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net core/cs_we_AND_247_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp bclk_dll_mod/dcm_sp_inst,
consult the device Data Sheet.
DRC detected 0 errors and 2 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "novena_eim.bit".
Bitstream generation is complete.
. /opt/Xilinx/14.3/ISE_DS/settings64.sh; \
promgen -w -s 8192 -p mcs -o novena_eim.mcs -u 0 novena_eim.bit
. /opt/Xilinx/14.3/ISE_DS/common/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common
. /opt/Xilinx/14.3/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.3/ISE_DS/EDK
. /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery/.settings64.sh /opt/Xilinx/14.3/ISE_DS/common/CodeSourcery
. /opt/Xilinx/14.3/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.3/ISE_DS/PlanAhead
. /opt/Xilinx/14.3/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.3/ISE_DS/ISE
Release 14.3 - Promgen P.40xd (lin64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
0x16a674 (1484404) bytes loaded up from 0x0
Using user-specified prom size of 8192K
Writing file "novena_eim.mcs".
Writing file "novena_eim.prm".
Writing file "novena_eim.cfi".
real 17m22.756s
user 17m20.276s
sys 0m7.891s
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