[Cryptech Tech] Tesing of entropy sources in FPGAs

[Bernd Paysan]

Am Dienstag, 1. Juli 2014, 16:47:14 schrieb Bernd Paysan:
> * Reduce the sampling frequency so that no obvious peak is showing up in
> the  FFT: This maximises the entropy you can get out of this source.

Coorection: this maximises the entropy per bit.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://bernd-paysan.de/
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