[Cryptech Tech] Padding in hash cores?

[Joachim Strömbergson]

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Aloha!

The current HW implementation of SHA-256 (and SHA-1) do not pad the
message, but expects that the caller pads the message. Basically the
core supports an initial message block followed by zero or more message
blocks. For each block the core calculates and returns the digest. The
caller therefore needs to pad the last block according to FIPS 180-4 if
the result are going to be compatible with the standard.

I've seen the padding as a low complexity operation done at the end of a
message that SW can handle, SW that probably anyway needs to keep track
of the message length. This separation removes some complexity in the HW
by being message length agnostic.

But is this what SW would expect from a HSM providing hashing? I would
assume that a HSM containing both HW and SW parts would do this
separation of duties. When you (SW developers) in the project think
about the architecture, what are your expectations?

Do you want to handle the padding or just divide the messsage into
blocks and for the final block just inform the core that it is the last
block and how much data that block contains?

Adding padding functionality is not a very big thing. I basically need
to add "final" and "length" ports to allow the caller to inform the core
that the current block loaded is the final block and should be padded
with a variable number of zeros and the length information. Basicallly
an extra MUX and some gates in between the input to the block word
scheduler.

We could add this later to the cores, but getting these kinds of
partitioning decisions done early is imho good.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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