[Cryptech Tech] Micro-status report from Göteborg workshop

[Rob Austein]

Rev2 noise board with blinky-lights works on Novena, seems to be
generating entropy.  Testing continues.

Some design discussion of the C/Verilog (green/blue) interface: memory
mapped, ring buffers if needed, ability to swap state in and out of
cores so that we can support, eg, multiple PKCS #11 sessions (we think
this is a requirement, icky though it is).

Some progress on EIM: problem not fully solved yet, but we have
reliable read/write between CPU and FPGA across clock domains (FPGA
running at 50MHz, CPU/EIM running at 133MHz).  Currently looking for
various possible race conditions.  Testing continues.