[Cryptech Tech] Some info on the Verilog HW description language

[Joachim Strömbergson]

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Aloha!

Joachim Strömbergson wrote:
> Some things to know is that all blocks (processes and assignments)
> runs concurrently (to simulate reality).

To clarify: When simulating the design in a simulator, this is the
simulated behaviour. When running the design through the FPGA tools we
get a netlist where the hardware is like this.

An AND-gate for example will always react as soon as its inputs are
updated, just like all other logic gates. And the registers in the FPGA
will sample their inputs in synch with their clock. All at the same time
all over the chip.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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