<!DOCTYPE html><html><head><title></title><style type="text/css">p.MsoNormal,p.MsoNoSpacing{margin:0}</style></head><body><div>Thanks Paul! Will incorporate.<br></div><div><br></div><div><br></div><div>On Wed, Mar 25, 2020, at 9:04 PM, Paul Selkirk wrote:<br></div><blockquote type="cite" id="qt"><div>I'd split the first paragraph, and fill out the sentence fragment.<br></div><div>Second sentence of the first paragraph is new, everything else is<br></div><div>reformatting:<br></div><div><br></div><div>Progress on the CrypTech project has slowed considerably due to a<br></div><div>serious slow-down in funding. However, we were still able to implement<br></div><div>several FPGA enhancements, which added up to a more than 10x improvement<br></div><div>in RSA signing speed.<br></div><div><br></div><div>At the end of 2018, CrypTech wrapped up its time under the<br></div><div>administrative umbrella of NorduNet and SUnet and moved to the Commons<br></div><div>Conservancy/NLnet Foundation. 2019 was CrypTech’s first full year as<br></div><div>part of the Commons Conservancy.<br></div><div><br></div><div>Although CrypTech’s first commercial user, Diamond Key Security, NFP,<br></div><div>shipped prototypes in 2018 and was well on its way to completing a<br></div><div>commercial offering, it was unable to get sufficient funding to ship a<br></div><div>supported product and ended up closing its doors. Acquiring funding<br></div><div>remains the critical issue for CrypTech to continue and advance.<br></div><div><br></div><div><br></div><div>Under Current Technical Status, add something like the following:<br></div><div><br></div><div>Significant developments in the FPGA include:<br></div><div><br></div><div>- Synchronous clocking for the FMC bus and the FPGA cores eliminates<br></div><div>polling on the bus, and simplifies the design.<br></div><div><br></div><div>- A new ModExpNG ("next generation") core moves most of the RSA signing<br></div><div>operation to hardware.<br></div><div><br></div><div>- A new keywrap core moves most of the AES key wrap/unwrap operation to<br></div><div>hardware.<br></div><div><br></div><div>Taken together, these take RSA signing speed from less than 8 sig/sec<br></div><div>with a 2048-bit key, to more than 87 sig/sec. Furthermore, a dedicated<br></div><div>RSA signer (without ECDSA support) can push this past 116 sig/sec. We<br></div><div>believe that further gains are possible without too much effort.<br></div><div><br></div><div>paul<br></div><div><br></div><div>_______________________________________________<br></div><div>Core mailing list<br></div><div>Core@cryptech.is<br></div><div>https://lists.cryptech.is/listinfo/core<br></div><div><br></div></blockquote></body></html>