[Cryptech Core] Draft agenda for restart meeting

[Joachim Strömbergson]

Aloha!

On 2019-09-25 17:24, Phil Roberts wrote:
> I've put up a draft agenda on Etherpad for our restart meeting next Thursday: https://tid.isoc.org/pad/p/cryptech-restart-discussion-10-03/2019
> Feel free to edit it, add things, say some things aren't worth talking about, etc.

Trying to access it, but get:
"Cannot GET /p/cryptech-restart-discussion-10-03/2019"

What needs to be on that list is the project activities we stated in the
NGI_Trust application:

* Updated Cryptech V1 KiCAD design as baseline for V2.
* New SW core functionality - selected SW changes
* V2 board design
* V2 board manufacturing and validation
* SW for V2.

So we need to talk about the difference between V1 and V2 (partitioning,
new functionality, board issues etc) and what changes this implies. And
then plan time and people that will do the tasks.

The list above contains very little that explicitly relates to FPGA
functionality. But new SW functionality and partitioning as well as
board changes will of course involve FPGA work too. Design objects I
would like to see on the agenda are:

* New ModExp cores completed and integrated

* RISC-V core to allow moving CRT and other SW based computations from
the STM32 to inside the FPGA and allow us to never have any cleartext
key material outside the FPGA.

* FPGA based Master Key Memory to allow fast erasure and tamper response
that is not based on someone pushing the panic button.


We also need to discuss the timeplan. What is stated by the project in
the NGI_Trust application is that everything should be completed by
August 2020. As the owner of the neck which would be hanged if we don't
deliver, I would very much like to see us striving to meet this deadline.

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson
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