[Cryptech Core] Proposal for new FPGA architecture

[Peter Stuge]

Joachim Strömbergson wrote:
> What I propose is to add API functionality to the core selector that
> would expose a DMA mechanism with from-to copy functionality to the MCU.

Do you mean DMA only within the FPGA, between different cores?

Maybe, but I think this does require core_selector to change a fair
bit beyond just the DMA API, because it will also have to deal with SW
commands that conflict with ongoing DMA operations. Rife for races.


> The core selector would also have a two port buffer memory. This would
> allow SW to read or write the contents of the memory while the DMA
> engine is performing copy operations between the buffer memory and a core.

Why would the contents be exposed to the outside? Isn't the point of
a DMA engine in the FPGA to keep everything within the FPGA?


> the MCU could of course make the DMA first write the sensitive data to a
> core memory, and then write it to the memory area it can access (or in
> the core directly).

Operations that may write to SW-accessible memory could be whitelisted,
with no key-disclosing operations on that list.


> Today it is generated by a python program based on the core
> configuration. This generator would have to be modified and possibly be
> a bit more complicated to include its own API. implement a MUX that can
> be controlled by the DMA engine. And instantiate the the buffer memory
> and the DMA engine.

Why the MUX and buffer memory?

How about core_selector simply keeping track of what core is busy,
and either stalling or NAKing requests to that core?


//Peter