[Cryptech Core] Xilinx Zync devices for possible next Cryptech HSM

[Peter Stuge]

Joachim Strömbergson wrote:
> > Please clarify exactly what allows performance gains, if core clock
> > stays near same order of magnitude?
> 
> Today we do *a lot* of transfer over the FPGA bus.

To set up a core with config and data, and then to poll for completion,
right?


> > Yes, the bare metal software environment on the M4 is a bit lame,
> > but it also does not have a whole lot to do.
> 
> Well, the M4 actually ha quite a lot do do.

Aha! That's already a good hint. Maybe some tasks could be moved over
to the FPGA?


> > What are the actual bottlenecks?
> 
> That is a very good question. I posted a pretty lengthy email with some
> analysis and more questions related to current status of the performance
> improvements, profiling etc. With a flurry of zero responses.

I read it just now, sorry for not getting to it sooner, I guess it's
a bit open ended, but indeed, profiling seems the next logical step.

I feel that the M4 layers and layers of abstraction are absurd for the
overall fairly simple tasks it needs to do.

Profiling is probably part reading assembly, part turning on LEDs and
measuring times between states with a scope.

Moving data on FMC can't require calculation at run time, that's an
architecture problem to solve. For flexibility one lookup does the
trick. Then just clock out words. The receiving buffer should be
circular and destination address auto-incremented, so that no bus
time is needed for redundant address information. I guess this is
already the case?


//Peter