[Cryptech Core] regarding speed grades and clock speeds

[Joachim Strömbergson]

Aloha!

Phil asked how FPGA speed grades would provide possible clock speeds for
the whole Cryptech FPGA design. I've done some builds just to see the
difference for the fmc_fix branch of Releng.

The version of the branch I have seems to lack some of the optimization
work and doesn't meet timing for speed grade -1 (which we are able to
do). But the results should at least give an indication the difference
in clock speeds reachable for a complete FPGA design with different
speed grades.

Speed grade -1:
Design statistics:
   Minimum period:  24.791ns (Maximum frequency:  40.337MHz)


Speed grade -2:
Design statistics:
   Minimum period:  11.538ns (Maximum frequency:  86.670MHz)


Speed grade -3:
Design statistics:
   Minimum period:  10.105ns (Maximum frequency:  98.961MHz)


-- 
Med vänlig hälsning, Yours

Joachim Strömbergson
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