[Cryptech Core] capacity/performance numbers?

[Pavel Shatov]

On 15.06.2016 21:17, Rob Austein wrote:
>
> Performance numbers on the Novena were not encouraging.  The Alpha
> has a slower CPU but a faster FPGA, so the overall mix will likely
> change, at least for RSA; ECDSA will likely change significantly once
> Pavel completes his Verilog EC point multiplier, but we don't expect
> to have that in time for Berlin.
>

It's difficult to predict the peak performance of the FPGA. We have a 
device, that is faster than in Novena, but so far we clock it at pretty 
conservative 50 MHz. We have not tried pushing the system frequency to 
its limit. To further complicate things, the maximum operating frequency 
will be different for different sets of cores. Smaller designs will 
likely run faster.

We also have a larger (~5x) device than the one in Novena, and in FPGA 
one can easily trade space for speed. I think, we can crunch say 10 
ModExp cores into the FPGA and make it run 10 parallel RSA operations at 
once. This will of course require some kind of dispatcher in the STM32 
processor than will monitor and load/unload all these cores. Again, we 
have not tried that simultaneous operation so far.


-- 
With best regards,
Pavel Shatov