[Cryptech Core] Fwd: SV: SV: SV: SV: SV: SV: SV: SV: Från BitSim...

[Jacob]

 > Leif Johansson wrote on Tue Jun 2 08:44:56 UTC 2015
 > Latest offer from Bitsim. About 70k still.

In addition to the other mail-list members' response to that proposal, I 
would like to add the following:

1. BitSim has not polished enough their time estimates:

They say "This assignment will last around 3-4 months" (barring 
complexities), but also itemize the following:

    - 1 week to deliver "System Design Spec"
    - 2 months for "first version of the board schematic for review"
    - 2 months after schematic review "delivers the first version of
      the PCB-layout for review"
    - 2 weeks for board assembly

    - (They miss here testing the assembled boards with their test
      vectors to verify that all components talk to each other at the
      desired environmental envelope).
    - HW SW FPGA Integration phase (not clear if included in the overall
      time estimate).

Although they do day that they might time-overlap some schematic design 
with layout, or test-plan generation with schematic, this has cost 
implications due to parallel design inefficiencies. The itemized list 
comes to minimum of 5 months engagement time, barring any mid-course 
changes and any of their "Risk" section effects.

2. I feel a bit apprehensive about their "Risks" paragraph:
    - The board re-spin due to "high speed design".
    - The integration phase

I feel that these 2 should be part of their responsibility as a 
professional design house. I may understand the effect on the time 
table, but not on the cost to the customer of such not-overly-complex board.

3. In view of the above, I think that the group should expect to see 
closer to 100K$ project charge.

If there is an interest among the group members, I am positive that I 
can find a professional design house among my customers who would offer 
a fixed price quotation at a lower cost (including a few assembled 
prototype boards running operational test routines), without any 
associated re-spin or integration "risks".

Jacob