[Cryptech Core] alpha schematics

[Pavel Shatov]

On 15.12.2015 5:32, Peter Stuge wrote:
>
> Page 13 says "PROM is write-protected by default, to disable write
> protection (..), jumper must be inserted" - but FPGA_PROM_W_N can
> also drive /W high to disable SPI flash write-protect.

Good catch, thank you! The signal FPGA_PROM_W_N itself is not supposed 
to be connected anywhere. As far as I remember, I labeled it to just 
have a sane name for that net, not just $net_1234. Maybe it will be 
better to make net name in this place invisible and also delete part of 
wire extending to the left (picture attached).

> Analog switches aren't strictly neccessary for the unidirectional
> signals, but also don't cause any problem as long as their bandwidth
> is high enough for the digital switching.

I'm also afraid, that "Analog switch to boot FPGA from config memory, or 
from ARM" is misleading.

FPGA has built-in config memory, that is volatile. There must be some 
external non-volatile memory, where the bitstream will be stored. Every 
time FPGA is powered up, config bitstream must be loaded from that 
external memory into FPGA's internal volatile latches. Now FPGA can try 
do this itself automatically (master mode), or it can just sit and wait 
for someone to send it the bitstream (slave mode).

Novena has the second variant. The bitstream is stored on the SD card, 
when we run configure script i.MX processor reads the bitsream from disk 
and directly sends it to the FPGA to configure it.

If I understand everything correctly, we want Alpha board to implement 
the first variant. The FPGA will automatically load bitstream from 
config memory. STM32 processor will not be able to directly configure 
FPGA anymore, it will only be able to re-write config memory with new 
bitstream (if allowed by insertion of jumper) and tell FPGA to re-load 
bitstream from config memory. Is this what we actually want?

Given that the above assumption is valid, the problem is that we have 
one SPI slave (config memory) and two SPI masters (FPGA and STM32). I 
think, somewhat better solution than analog switch will be to use 
3-stateable buffer, such as 74AHC244. It has a pair of 4-bit buses, 
exactly what we need for two SPI interfaces.

-- 
With best regards,
Pavel Shatov

-------------- next part --------------
A non-text attachment was scrubbed...
Name: fpga_config_mem.png
Type: image/png
Size: 36305 bytes
Desc: not available
URL: <https://lists.cryptech.is/archives/core/attachments/20151215/6a22a052/attachment-0001.png>