[Cryptech Core] multiple offers...

[Jacob]

Leif,

Some comments re the 2 offers:

1. During the majority of HW projects dev, there is a clear separation 
between the Design and the Layout tasks - different skills and groups. 
Are the 2 vendors willing to split their quote so that Cryptech can go 
along with just one task, namely Design (+ test, integration etc.)?

One advantage to such a separation, in addition to costs, is that route 
will force the circuit/schematic designer to fully document his design 
intent so we end up with a matched schematic to layout ( I saw many 
cases where companies did both schematic and layout in house, and during 
the layout phase the design engineer asked Layout to add just a small 
resistor here and a small capacitor there - on the fly - without 
spending the time to follow proper procedures of generating a schematic 
ECO (Engineering Change Order) and feed the new netlist into the layout).

2. Neither offer talks about Signal Integrity analysis. The DDR3 traces 
must be done with the help of such tools to ascertain proper topology 
and trace characteristics.
Bitsim says that they will charge for any extra tool that is needed, so 
they may charge for the SI tools - very expensive proposition. Mentor 
licensing is finely grained, and having mentor Expedition license does 
not mean having Mentor Hyperlynx license for SI work. And the Hyperlynx 
license, in turn, has many sub-licenses (at cost) for each and every 
small feature in the program.

3. Who will pay for design re-spin if there are flaws or missing 
functionality in the finished design? Cryptech strength is not in 
electronic design, but it has the responsibility to approve and accept 
the design made by the chosen vendor. I suggest to move more 
responsibility to the vendor, by having Cryptech just specifying 
functional requirements desired from the board and let the vendor bear 
the responsibility to achieve that.

Jacob