[Cryptech Core] Xilinx FPGA timing expert

[Joachim Strömbergson]

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Aloha!

I would like to propose to try and bring in a FPGA expert to help us
solve the problems we are seeing with the EIM interface and clocking in
the Novena. The one person that I know is really, really good ay timing
issues, clocking in Xilinx FPGAs is Tryggve Mathiesen at InformAsic. He
has solved these issues before and is certified educator by Xilinx on
Xilinx design and clocking. He knows the specifics of Xilinx FPGAs.

Should I talk to him and see if he would be able to assist us with the
eim issues?

I'm confident that he would be able to help us solve the
problems. This should also not only benefit the Cryptech project, but
the Novena projects and any other projects that tries to build FPGA
designs that talks to the Freescale CPU on the Novena via the EIM interface.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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