[Cryptech Core] two presos

[Randy Bush]

> Slide 11: "later allow". Something missing. Later possible ASIC
> implementation or something perhaps.

easy

> Slide 26: If you want to emphasize state in the TRNG you could also add
> a loop within the mixer to illustrate that we don't restart the mixer,
> but instead treat the entropy as part of a very long message from which
> we extract digests for after each new block added. And that we need
> digests from two consecutive blocks (thus 2kbit entropy) to do reseed of
> the csprng. Unless that is way too much detail.

not easy.  will work on it

> Slide 33: Should we perhaps remove "MD5" from the blue layer?

good question.  suspect folk still want/need it.  otoh, it is a bs
attractor.  so removal may be good.

> Regarding finding a 486. Another option that might be worth mentioning
> is that there are other x86 cpu vendors (Via, AMD) as well as other ISAs
> (ARM, Tizen, MIPS, RISC-V, OpenRISC, SPARC/LEON). Some implementations
> of them might be suspect, but probably not by the same actor. Some of
> them are open source (spec and implementation) and we could build some
> trust by not only do Wheeler-compilation, but also use multiple ISAs, at
> least for testing.

it may depend on how much tin foil one is wearing.  think of how you
would attack this.  still thinking.

> HDL is normally an abbreviation for "Hardware Decription Language".

thanks.

> I would also add that there exists no open toolchain from Verilog source
> to FPGA bitstream. Sooner rather than later you end up in the vendor
> black box.

> Glad to see the turtles. ;-)

they may have to go.  rather culturally specific.  shame.

randy