[Cryptech Core] Status re Novena?

[Paul Selkirk]

On 08/22/2014 02:49 AM, Joachim Strömbergson wrote:
> What is the status regarding the Novena boards? Has there been any
> progress in getting connectivity between SW on the CPU and HW in the
> FPGA - via I2C or EIM?
> 
> And are there any info/news on getting those general purpose peripheral
> boards?

For the main part of this, I was remiss in not sharing Bunnie's reply
during the face-to-face (below).

As to the second question, I've got a working coretest with I2C, and
rewritten user-side test code, which I need to commit.

For EIM, there are several Novena projects on github that include
relevant Verilog, which I will be looking at over the course of this
weekend's 1000+ km road trip to take my daughter back to college.

				paul

-------- Forwarded Message --------
Subject: Re: novena fpga
Date: Mon, 28 Jul 2014 16:57:27 +0000
From: bunnie <bunnie at bunniestudios.com>
To: Paul Selkirk <paul at psgd.org>, xobs <smcross at gmail.com>
CC: Randy Bush <randy at psg.com>

Hi Paul,

Answers in-line below.

On 07/28/2014 04:02 PM, Paul Selkirk wrote:
> Gentlemen -
>
> The Cryptech project is starting to use the Novena PVT board as a
> development/prototyping platform, so we are very interested in the
> physical and bus interfaces to the FPGA.
>
> 1. We would like to use the General-Purpose Breakout Board to
> sample entropy sources (zener diodes and the like). When will this
> board be available, and how much will it cost? Initially, we'd like
> to get 4 (one for each of the Novenas we currently have in hand).

Pricing hasn't been set but we'll be offering that as one of the items
for sale on Crowd supply after we start shipping mainboards in
November. Probably they will cost around $30-$40; I didn't pick the
cheapest ADC or DACs for the implementation.

>
> 1a. When will the next-generation Novena board be available?

You can pre-order now on Crowd Supply. There is about a 16 week lead
time to build them, so if you have a large demand it would be good to
know. We are only over-building a little bit because they are really
expensive boards to inventory; probably we will only make 100 units
over the original crowd supply campaign available and if those sell
out it could be 16 weeks before another set is available.

>
> 2. We'd like to use the EIM bus for high-speed access to both the
> entropy sources and the cores that implement the crypto primitives.
> Is there a Verilog driver for EIM, or is it just the kernel module
> in the novena-scope-drivers project? (Not a deal-breaker, since
> this part of the project is inherently system-specific.)

There is verilog code on the FPGA side that does the EIM bus, and we
have multiple implementations for modules to talk to the EIM. It can
be as simple as just doing a mmap() read/write to a window in
/dev/kmem, but the bandwidth can be fairly slow doing that (limited to
a couple megabytes per second at best). If you need burst access with
higher bandwidth we have an implementation we prepared for use with
the oscilloscope module that goes a good bit faster (iirc at least
10x-20x faster), but it's also a lot more complicated both on the
Verilog side and the kernel driver side as we have to set up data
streams.

thanks,

-b.

>
> paul