[Cryptech Core] Interface questions?

[Joachim Strömbergson]

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Aloha!

I have started to (mentally) write on a description/specification for a
RNG with support for two entropy sources - one internal and one
external. One of the first things I want to do is a create a simple
register map/API to have something to discuss.

When it comes to the basic protocol I think we should follow Wishbone:
http://opencores.org/opencores,wishbone

Using Wishbone will allow not only the usage of the OpenRISC processor,
but also a lot of other cores such as GPIO, Timers, UARTS, Ethernet MACs
etc. There is in fact a complete reference platform that one can use and
build on:

http://opencores.org/or1k/ORPSoC


I'm thinking of getting on of these:
http://www.orsoc.se/?page_id=449

This would mean that we at least for a start would be using 32-bit wide
data busses and big endian (which is the default for OpenRISC albeit it
can be switched to little endian too). Is that ok for everyone?

I know this is pretty low level stuff, but in order to do some spec work
I need to have this assumptions checked.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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