[Cryptech-Commits] [core/util/keywrap] 31/95: Connected the keymem dut into the testbench.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository core/util/keywrap.

commit caa7950bacb13e253a7761e34d536c104d4ff11e
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Jun 29 14:35:58 2018 +0200

    Connected the keymem dut into the testbench.
---
 src/tb/tb_keywrap_mem.v | 65 ++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 54 insertions(+), 11 deletions(-)

diff --git a/src/tb/tb_keywrap_mem.v b/src/tb/tb_keywrap_mem.v
index 6203f0e..6e4a056 100644
--- a/src/tb/tb_keywrap_mem.v
+++ b/src/tb/tb_keywrap_mem.v
@@ -39,12 +39,45 @@
 
 module tb_keywrap_mem();
 
+  //----------------------------------------------------------------
+  // Parameters.
+  //----------------------------------------------------------------
   parameter CLK_HALF_PERIOD = 1;
   parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
 
+
+  //----------------------------------------------------------------
+  // Variables, regs and wires.
+  //----------------------------------------------------------------
   integer cycle_ctr;
-  reg tb_sys_clk;
-  reg tb_reset_n;
+  reg [31 : 0]  error_ctr;
+  reg [31 : 0]  tc_ctr;
+
+  reg           tb_clk;
+  reg           tb_api_we;
+  reg [13 : 0]  tb_api_addr;
+  reg [31 : 0]  tb_api_wr_data;
+  wire [31 : 0] tb_api_rd_data;
+  reg           tb_core_we;
+  reg [12 : 0]  tb_core_addr;
+  reg [63 : 0]  tb_core_wr_data;
+  wire [63 : 0] tb_core_rd_data;
+
+
+  //----------------------------------------------------------------
+  // Device Under Test.
+  //----------------------------------------------------------------
+  keywrap_mem dut(
+                  .clk(tb_clk),
+                  .api_we(tb_api_we),
+                  .api_addr(tb_api_addr),
+                  .api_wr_data(tb_api_wr_data),
+                  .api_rd_data(tb_api_rd_data),
+                  .core_we(tb_core_we),
+                  .core_addr(tb_core_addr),
+                  .core_wr_data(tb_core_wr_data),
+                  .core_rd_data(tb_core_rd_data)
+                 );
 
 
   //----------------------------------------------------------------
@@ -55,7 +88,7 @@ module tb_keywrap_mem();
   always
     begin : clk_gen
       #CLK_HALF_PERIOD;
-      tb_sys_clk = !tb_sys_clk;
+      tb_clk = !tb_clk;
     end // clk_gen
 
 
@@ -79,19 +112,29 @@ module tb_keywrap_mem();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  initial
+  task init_sim;
     begin
-      cycle_ctr     = 0;
-      tb_sys_clk    = 0;
-      tb_reset_n    = 0;
+      cycle_ctr = 0;
+      tb_clk    = 0;
+    end
+  endtask // init_sim
+
 
-      #(CLK_PERIOD * 10);
+  //----------------------------------------------------------------
+  // main
+  //----------------------------------------------------------------
+  initial
+    begin : main
+      $display("   -= Testbench for Keywrap memory started =-");
+      $display("    =========================================");
+      $display("");
 
-      tb_reset_n    = 1;
+      init_sim();
 
-      #(CLK_PERIOD * 10);
+      $display("");
+      $display("*** Keywrap memory simulation done. ***");
       $finish;
-    end
+    end // main
 
 endmodule // tb_keywrap_mem