[Cryptech-Commits] [core/math/modexpng] 40/92: Added support for non-CRT mode. Further refactoring.
git at cryptech.is
git at cryptech.is
Sat Mar 14 18:19:19 UTC 2020
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paul at psgd.org pushed a commit to branch master
in repository core/math/modexpng.
commit 69b5d9f65cf49adbc1c1850fa2c4757199008717
Author: Pavel V. Shatov (Meister) <meisterpaul1 at yandex.ru>
AuthorDate: Mon Oct 21 15:10:44 2019 +0300
Added support for non-CRT mode. Further refactoring.
---
bench/tb_core_full_512.v | 2 +-
rtl/modexpng_core_top.v | 4 ++++
rtl/modexpng_general_worker.v | 2 +-
rtl/modexpng_io_manager.v | 13 ++++++++++---
rtl/modexpng_uop_engine.v | 9 ++++-----
rtl/modexpng_uop_rom.v | 38 +++++++++++++++++++++++++++++++++++---
6 files changed, 55 insertions(+), 13 deletions(-)
diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v
index 75accff..e2604f0 100644
--- a/bench/tb_core_full_512.v
+++ b/bench/tb_core_full_512.v
@@ -335,7 +335,7 @@ module tb_core_full_512;
//
task core_set_input_2;
begin
- //for (_w=0; _w< TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd2, BANK_IN_2_D, { _w[6:0]}, D [_w]);
+ for (_w=0; _w< TB_NUM_WORDS_N; _w=_w+1) bus_write(2'd2, BANK_IN_2_D, { _w[6:0]}, D [_w]);
for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P, {1'b0, _w[5:0]}, P [_w]);
for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P, {1'b1, _w[5:0]}, DP [_w]);
for (_w=0; _w< TB_NUM_WORDS_PQ; _w=_w+1) bus_write(2'd2, BANK_IN_2_P_FACTOR, { _w[6:0]}, P_FACTOR[_w]);
diff --git a/rtl/modexpng_core_top.v b/rtl/modexpng_core_top.v
index 0c72478..a991c61 100644
--- a/rtl/modexpng_core_top.v
+++ b/rtl/modexpng_core_top.v
@@ -323,7 +323,9 @@ module modexpng_core_top
wire [ WORD_EXT_W -1:0] io_narrow_y_data_y; //
wire [ WORD_W -1:0] wrk_rd_narrow_x_data_x_lsb = wrk_rd_narrow_x_data_x[WORD_W-1:0];
+ wire [ WORD_W -1:0] wrk_rd_narrow_y_data_x_lsb = wrk_rd_narrow_y_data_x[WORD_W-1:0];
wire [ WORD_W -1:0] wrk_rd_narrow_x_data_y_lsb = wrk_rd_narrow_x_data_y[WORD_W-1:0];
+ wire [ WORD_W -1:0] wrk_rd_narrow_y_data_y_lsb = wrk_rd_narrow_y_data_y[WORD_W-1:0];
//
@@ -735,7 +737,9 @@ module modexpng_core_top
.io_out_dout (io_out_data),
.wrk_narrow_x_din_x_lsb (wrk_rd_narrow_x_data_x_lsb),
+ .wrk_narrow_y_din_x_lsb (wrk_rd_narrow_y_data_x_lsb),
.wrk_narrow_x_din_y_lsb (wrk_rd_narrow_x_data_y_lsb),
+ .wrk_narrow_y_din_y_lsb (wrk_rd_narrow_y_data_y_lsb),
.ladder_steps (io_mgr_ladder_steps),
.ladder_d (io_mgr_ladder_d),
diff --git a/rtl/modexpng_general_worker.v b/rtl/modexpng_general_worker.v
index cedbee9..4202066 100644
--- a/rtl/modexpng_general_worker.v
+++ b/rtl/modexpng_general_worker.v
@@ -37,7 +37,7 @@ module modexpng_general_worker
input [ BANK_ADDR_W -1:0] sel_narrow_out;
input [ BANK_ADDR_W -1:0] sel_wide_in;
input [ BANK_ADDR_W -1:0] sel_wide_out;
-
+
input [ UOP_OPCODE_W -1:0] opcode;
input [ OP_ADDR_W -1:0] word_index_last;
diff --git a/rtl/modexpng_io_manager.v b/rtl/modexpng_io_manager.v
index da2bdac..5bce191 100644
--- a/rtl/modexpng_io_manager.v
+++ b/rtl/modexpng_io_manager.v
@@ -53,7 +53,9 @@ module modexpng_io_manager
io_out_dout,
wrk_narrow_x_din_x_lsb,
+ wrk_narrow_y_din_x_lsb,
wrk_narrow_x_din_y_lsb,
+ wrk_narrow_y_din_y_lsb,
ladder_steps,
ladder_d,
@@ -125,7 +127,9 @@ module modexpng_io_manager
output [ WORD_W -1:0] io_out_dout;
input [ WORD_W -1:0] wrk_narrow_x_din_x_lsb;
+ input [ WORD_W -1:0] wrk_narrow_y_din_x_lsb;
input [ WORD_W -1:0] wrk_narrow_x_din_y_lsb;
+ input [ WORD_W -1:0] wrk_narrow_y_din_y_lsb;
input [ BIT_INDEX_W -1:0] ladder_steps;
output ladder_d;
@@ -457,6 +461,9 @@ module modexpng_io_manager
//
wire [WORD_EXT_W -1:0] io_in_dout_mux = {{(WORD_EXT_W-WORD_W){1'b0}}, sel_aux_is_1 ? io_in_1_din : io_in_2_din};
+ wire [WORD_W -1:0] wrk_narrow_xy_din_x_mux_lsb = sel_aux == UOP_AUX_1 ? wrk_narrow_x_din_x_lsb : wrk_narrow_y_din_x_lsb;
+ wire [WORD_W -1:0] wrk_narrow_xy_din_y_mux_lsb = sel_aux == UOP_AUX_1 ? wrk_narrow_x_din_y_lsb : wrk_narrow_y_din_y_lsb;
+
always @(posedge clk) begin
//
wide_x_din_x <= WORD_EXT_DNC;
@@ -476,12 +483,12 @@ module modexpng_io_manager
IO_FSM_STATE_EXTRA,
IO_FSM_STATE_LATENCY_POST1: begin
//
- if (opcode_is_input_wide && sel_crt_is_x) {wide_x_din_x, wide_y_din_x} <= {2{io_in_dout_mux}}; // TODO: Make external ports smaller (WORD_W, not WORD_EXT_W)??
+ if (opcode_is_input_wide && sel_crt_is_x) {wide_x_din_x, wide_y_din_x} <= {2{io_in_dout_mux}};
if (opcode_is_input_wide && sel_crt_is_y) {wide_x_din_y, wide_y_din_y} <= {2{io_in_dout_mux}};
if (opcode_is_input_narrow && sel_crt_is_x) {narrow_x_din_x, narrow_y_din_x} <= {2{io_in_dout_mux}};
if (opcode_is_input_narrow && sel_crt_is_y) {narrow_x_din_y, narrow_y_din_y} <= {2{io_in_dout_mux}};
//
- if (opcode_is_output) out_dout <= sel_crt_is_x ? wrk_narrow_x_din_x_lsb: wrk_narrow_x_din_y_lsb;
+ if (opcode_is_output) out_dout <= sel_crt_is_x ? wrk_narrow_xy_din_x_mux_lsb : wrk_narrow_xy_din_y_mux_lsb;
//
end
//
@@ -490,7 +497,7 @@ module modexpng_io_manager
if (opcode_is_input_narrow && sel_crt_is_x && sel_in_needs_extra) {narrow_x_din_x, narrow_y_din_x} <= {2{io_in_dout_mux}};
if (opcode_is_input_narrow && sel_crt_is_y && sel_in_needs_extra) {narrow_x_din_y, narrow_y_din_y} <= {2{io_in_dout_mux}};
//
- if (opcode_is_output) out_dout <= sel_crt_is_x ? wrk_narrow_x_din_x_lsb : wrk_narrow_x_din_y_lsb;
+ if (opcode_is_output) out_dout <= sel_crt_is_x ? wrk_narrow_xy_din_x_mux_lsb : wrk_narrow_xy_din_y_mux_lsb;
//
end
//
diff --git a/rtl/modexpng_uop_engine.v b/rtl/modexpng_uop_engine.v
index a87d924..8ad2122 100644
--- a/rtl/modexpng_uop_engine.v
+++ b/rtl/modexpng_uop_engine.v
@@ -346,10 +346,10 @@ module modexpng_uop_engine
always @(uop_data_ladder, io_mgr_ladder_p, io_mgr_ladder_q, io_mgr_ladder_d)
//
case (uop_data_ladder)
- UOP_LADDER_00: uop_data_ladder_mux = 2'b00;
+ UOP_LADDER_00: uop_data_ladder_mux = 2'b00;
UOP_LADDER_11: uop_data_ladder_mux = 2'b11;
- UOP_LADDER_D: uop_data_ladder_mux = {io_mgr_ladder_d, ~io_mgr_ladder_d};
- UOP_LADDER_PQ: uop_data_ladder_mux = {io_mgr_ladder_p, io_mgr_ladder_q};
+ UOP_LADDER_D: uop_data_ladder_mux = {~io_mgr_ladder_d, io_mgr_ladder_d};
+ UOP_LADDER_PQ: uop_data_ladder_mux = { io_mgr_ladder_p, io_mgr_ladder_q};
endcase
reg [OP_ADDR_W-1:0] word_index_last_mux;
@@ -478,7 +478,7 @@ module modexpng_uop_engine
update_io_mgr_params(uop_data_crt, uop_data_aux, uop_data_sel_narrow_in, uop_data_sel_narrow_out, uop_data_opcode);
//
UOP_OPCODE_OUTPUT_FROM_NARROW: begin
- update_io_mgr_params(uop_data_crt, UOP_AUX_DNC, BANK_DNC, uop_data_sel_narrow_out, uop_data_opcode);
+ update_io_mgr_params(uop_data_crt, uop_data_aux, BANK_DNC, uop_data_sel_narrow_out, uop_data_opcode);
update_wrk_params(BANK_DNC, uop_data_sel_narrow_in, BANK_DNC, BANK_DNC, uop_data_opcode);
end
//
@@ -615,7 +615,6 @@ module modexpng_uop_engine
//
endcase
-
//
// UOP FSM Process
//
diff --git a/rtl/modexpng_uop_rom.v b/rtl/modexpng_uop_rom.v
index 5d6308c..c15f608 100644
--- a/rtl/modexpng_uop_rom.v
+++ b/rtl/modexpng_uop_rom.v
@@ -38,8 +38,8 @@ module modexpng_uop_rom
//
7'd015: data <= {UOP_OPCODE_PROPAGATE_CARRIES, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_NARROW_D }; //
//
- 7'd016: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_XM }; //
- 7'd017: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_YM }; //
+ 7'd016: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_XM }; //
+ 7'd017: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_YM }; //
//
7'd018: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_11, BANK_WIDE_E, BANK_NARROW_B, BANK_WIDE_C, BANK_NARROW_C }; //
//
@@ -108,7 +108,7 @@ module modexpng_uop_rom
//
7'd058: data <= {UOP_OPCODE_PROPAGATE_CARRIES, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_A, BANK_DNC, BANK_NARROW_A }; //
//
- 7'd059: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_A, BANK_DNC, BANK_OUT_S }; //
+ 7'd059: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_A, BANK_DNC, BANK_OUT_S }; //
//
// Non-CRT Mode (i.e. only when "D" is known)
//
@@ -126,6 +126,38 @@ module modexpng_uop_rom
7'd074: data <= {UOP_OPCODE_INPUT_TO_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_IN_1_M, BANK_DNC, BANK_NARROW_E }; //
7'd075: data <= {UOP_OPCODE_INPUT_TO_NARROW, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_IN_1_M, BANK_DNC, BANK_NARROW_E }; //
//
+ 7'd076: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_11, BANK_WIDE_A, BANK_NARROW_A, BANK_WIDE_B, BANK_NARROW_B }; //
+ 7'd077: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_11, BANK_WIDE_B, BANK_NARROW_B, BANK_WIDE_C, BANK_NARROW_C }; //
+ 7'd078: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_2, UOP_LADDER_11, BANK_WIDE_C, BANK_DNC, BANK_WIDE_D, BANK_NARROW_D }; //
+ //
+ 7'd079: data <= {UOP_OPCODE_PROPAGATE_CARRIES, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_NARROW_D }; //
+
+ 7'd080: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_XM }; //
+ 7'd081: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_D, BANK_DNC, BANK_OUT_YM }; //
+ //
+ 7'd082: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_11, BANK_WIDE_E, BANK_NARROW_B, BANK_WIDE_C, BANK_NARROW_C }; //
+
+ 7'd083: data <= {UOP_OPCODE_INPUT_TO_WIDE, UOP_CRT_X, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_IN_1_N_FACTOR, BANK_WIDE_A, BANK_DNC }; //
+ 7'd084: data <= {UOP_OPCODE_INPUT_TO_WIDE, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_DNC, BANK_DNC, BANK_IN_1_N_FACTOR, BANK_WIDE_A, BANK_DNC }; //
+
+ 7'd085: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_11, BANK_WIDE_C, BANK_NARROW_A, BANK_WIDE_D, BANK_NARROW_D }; //
+ 7'd086: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_2, UOP_LADDER_11, BANK_WIDE_A, BANK_DNC, BANK_WIDE_C, BANK_NARROW_C }; //
+
+ 7'd087: data <= {UOP_OPCODE_COPY_LADDERS_X2Y, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_WIDE_D, BANK_NARROW_D, BANK_WIDE_C, BANK_NARROW_C }; //
+
+ 7'd088: data <= {UOP_OPCODE_LADDER_INIT, UOP_CRT_DNC, UOP_NPQ_DNC, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_DNC, BANK_DNC, BANK_DNC }; //
+ 7'd089: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_D, BANK_WIDE_C, BANK_NARROW_C, BANK_WIDE_C, BANK_NARROW_C }; //
+ 7'd090: data <= {UOP_OPCODE_LADDER_STEP, UOP_CRT_DNC, UOP_NPQ_DNC, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_DNC, BANK_DNC, BANK_DNC }; //
+
+ 7'd091: data <= {UOP_OPCODE_CROSS_LADDERS_X2Y, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_WIDE_B, BANK_NARROW_B, BANK_WIDE_B, BANK_NARROW_B }; //
+
+ 7'd092: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_2, UOP_LADDER_11, BANK_WIDE_C, BANK_DNC, BANK_WIDE_D, BANK_NARROW_D }; //
+ 7'd093: data <= {UOP_OPCODE_MODULAR_MULTIPLY, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_1, UOP_LADDER_00, BANK_WIDE_B, BANK_NARROW_D, BANK_WIDE_A, BANK_NARROW_A }; //
+ //
+ 7'd094: data <= {UOP_OPCODE_PROPAGATE_CARRIES, UOP_CRT_DNC, UOP_NPQ_N, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_A, BANK_DNC, BANK_NARROW_A }; //
+ //
+ 7'd095: data <= {UOP_OPCODE_OUTPUT_FROM_NARROW, UOP_CRT_Y, UOP_NPQ_N, UOP_AUX_2, UOP_LADDER_DNC, BANK_DNC, BANK_NARROW_A, BANK_DNC, BANK_OUT_S }; //
+
default: data <= {UOP_OPCODE_STOP, UOP_CRT_DNC, UOP_NPQ_DNC, UOP_AUX_DNC, UOP_LADDER_DNC, BANK_DNC, BANK_DNC, BANK_DNC, BANK_DNC }; //
//
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