[Cryptech-Commits] [core/platform/common] 01/04: Added support for ModExpNG core: * new 'modexpng' target builds just the ModExpNG (this is mostly for various testing purposes) * new 'hsm_ng' target buils the plain old 'hsm' config + 1x ModExpNG

[git at cryptech.is]

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meisterpaul1 at yandex.ru pushed a commit to branch master
in repository core/platform/common.

commit 4f5c4453343430cce0067007deace5c1ddd7c29e
Author: Pavel V. Shatov (Meister) <meisterpaul1 at yandex.ru>
AuthorDate: Thu Jan 23 13:05:09 2020 +0300

    Added support for ModExpNG core:
     * new 'modexpng' target builds just the ModExpNG (this is mostly for various
       testing purposes)
     * new 'hsm_ng' target buils the plain old 'hsm' config + 1x ModExpNG
    
    Also added high-speed clock for the new clock manager.
---
 config/core.cfg | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/config/core.cfg b/config/core.cfg
index d6de1fa..6efc4af 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -36,8 +36,9 @@ modexp = modexpa7
 extra wires =
    output wire         mkm_sclk,
    output wire         mkm_cs_n,
-   input wire          mkm_do,
+   input  wire         mkm_do,
    output wire         mkm_di,
+   input  wire         core_clk,
 requires = mkmif/dummy-mkmif
 
 [board dev-bridge]
@@ -73,6 +74,10 @@ cores = trng
 # for testing just the Modular Exponentiation
 cores = modexp
 
+[project modexpng]
+# for testing just the ModExpNG
+cores = modexpng
+
 [project mkmif]
 # for testing just the Master Key Memory Interface
 cores = mkmif
@@ -86,6 +91,10 @@ cores = sha256 aes trng modexp
 # Make me one with everything, except we want two modexp cores for parallel CRT
 cores = sha1 sha256 sha512 aes trng modexp modexp mkmif ecdsa256 ecdsa384
 
+[project hsm_ng]
+# Make me one with everything, except we want the new ModExpNG core
+cores = sha1 sha256 sha512 aes trng modexp modexp modexpng mkmif ecdsa256 ecdsa384
+
 # [core] sections
 #
 # vfiles: A list of Verilog files to include in the vfiles list when
@@ -211,6 +220,37 @@ vfiles =
 	lib/lowlevel/artix7/dsp48e1_wrapper.v
 	lib/lowlevel/artix7/dsp48e1_wrapper_modexp.v
 
+[core modexpng]
+# ModExpNG for Xilinx Artix-7
+core blocks = 16
+block memory = yes
+error wire = no
+module name = modexpng_wrapper
+reset name = rst_n
+extra ports =
+      .clk_core(core_clk),
+vfiles =
+	../user/shatov/modexpng/rtl/modexpng_wrapper.v
+	../user/shatov/modexpng/rtl/modexpng_core_top.v
+	../user/shatov/modexpng/rtl/modexpng_general_worker.v
+	../user/shatov/modexpng/rtl/modexpng_mmm_dual.v
+	../user/shatov/modexpng/rtl/modexpng_reductor.v
+	../user/shatov/modexpng/rtl/modexpng_dsp_array_block.v
+	../user/shatov/modexpng/rtl/modexpng_io_block.v
+	../user/shatov/modexpng/rtl/modexpng_io_manager.v
+	../user/shatov/modexpng/rtl/modexpng_storage_block.v
+	../user/shatov/modexpng/rtl/modexpng_storage_manager.v
+	../user/shatov/modexpng/rtl/modexpng_uop_rom.v
+	../user/shatov/modexpng/rtl/modexpng_uop_engine.v
+	../user/shatov/modexpng/rtl/modexpng_recombinator_block.v
+	../user/shatov/modexpng/rtl/modexpng_recombinator_cell.v
+	../user/shatov/modexpng/rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v
+	../user/shatov/modexpng/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
+	../user/shatov/modexpng/rtl/modexpng_sdp_36k_x18_wrapper_xilinx.v
+	../user/shatov/modexpng/rtl/modexpng_sdp_36k_x16_x32_wrapper_xilinx.v
+	../user/shatov/modexpng/rtl/modexpng_sdp_36k_x32_x16_wrapper_xilinx.v
+	../user/shatov/modexpng/rtl/modexpng_tdp_36k_x16_x32_wrapper_xilinx.v
+
 [core modexps6]
 # ModExp for Xilinx Spartan-6
 core blocks = 4