[Cryptech-Commits] [user/shatov/modexpng] 09/14: Adapted to the changes in the DSP slice wrappers.
git at cryptech.is
git at cryptech.is
Tue Feb 11 13:04:31 UTC 2020
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meisterpaul1 at yandex.ru pushed a commit to branch master
in repository user/shatov/modexpng.
commit 58ad4d95d6de1f62bb3664e3782d8f6ae9c691f0
Author: Pavel V. Shatov (Meister) <meisterpaul1 at yandex.ru>
AuthorDate: Mon Feb 3 22:42:41 2020 +0300
Adapted to the changes in the DSP slice wrappers.
---
rtl/modexpng_general_worker.v | 16 ++++------------
rtl/modexpng_reductor.v | 18 +++++-------------
2 files changed, 9 insertions(+), 25 deletions(-)
diff --git a/rtl/modexpng_general_worker.v b/rtl/modexpng_general_worker.v
index 9a8824c..13b7aac 100644
--- a/rtl/modexpng_general_worker.v
+++ b/rtl/modexpng_general_worker.v
@@ -1070,9 +1070,7 @@ module modexpng_general_worker
`MODEXPNG_DSP_SLICE_ADDSUB dsp_inst_x_x
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (dsp_ce_x),
- .ce_c (dsp_ce_x),
+ .ce_abc (dsp_ce_x),
.ce_p (dsp_ce_x_dly),
.ce_ctrl (dsp_ce_x),
.ab (dsp_x_x_x),
@@ -1089,9 +1087,7 @@ module modexpng_general_worker
`MODEXPNG_DSP_SLICE_ADDSUB dsp_inst_y_x
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (dsp_ce_x),
- .ce_c (dsp_ce_x),
+ .ce_abc (dsp_ce_x),
.ce_p (dsp_ce_x_dly),
.ce_ctrl (dsp_ce_x),
.ab (dsp_y_x_x),
@@ -1108,9 +1104,7 @@ module modexpng_general_worker
`MODEXPNG_DSP_SLICE_ADDSUB dsp_inst_x_y
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (dsp_ce_y),
- .ce_c (dsp_ce_y),
+ .ce_abc (dsp_ce_y),
.ce_p (dsp_ce_y_dly),
.ce_ctrl (dsp_ce_y),
.ab (dsp_x_y_x),
@@ -1127,9 +1121,7 @@ module modexpng_general_worker
`MODEXPNG_DSP_SLICE_ADDSUB dsp_inst_y_y
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (dsp_ce_y),
- .ce_c (dsp_ce_y),
+ .ce_abc (dsp_ce_y),
.ce_p (dsp_ce_y_dly),
.ce_ctrl (dsp_ce_y),
.ab (dsp_y_y_x),
diff --git a/rtl/modexpng_reductor.v b/rtl/modexpng_reductor.v
index 0b4f62e..17fec1b 100644
--- a/rtl/modexpng_reductor.v
+++ b/rtl/modexpng_reductor.v
@@ -300,9 +300,7 @@ module modexpng_reductor
`MODEXPNG_DSP_SLICE_ADDSUB dsp_lsb_x
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (lsb_ce),
- .ce_c (lsb_ce),
+ .ce_abc (lsb_ce),
.ce_p (lsb_ce_dly),
.ce_ctrl (lsb_ce),
.ab (lsb_ax),
@@ -319,9 +317,7 @@ module modexpng_reductor
`MODEXPNG_DSP_SLICE_ADDSUB dsp_lsb_y
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (lsb_ce),
- .ce_c (lsb_ce),
+ .ce_abc (lsb_ce),
.ce_p (lsb_ce_dly),
.ce_ctrl (lsb_ce),
.ab (lsb_ay),
@@ -332,7 +328,7 @@ module modexpng_reductor
.carry_in_sel (DSP48E1_CARRYINSEL_CARRYIN),
.casc_p_in (),
.casc_p_out (lsb2msb_py_casc),
- .carry_out ()
+ .carry_out ()
);
always @(posedge clk or negedge rst_n)
@@ -387,9 +383,7 @@ module modexpng_reductor
`MODEXPNG_DSP_SLICE_ADDSUB dsp_msb_x
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (msb_ce),
- .ce_c (msb_ce),
+ .ce_abc (msb_ce),
.ce_p (msb_ce_dly1),
.ce_ctrl (msb_ce),
.ab (msb_ax),
@@ -406,9 +400,7 @@ module modexpng_reductor
`MODEXPNG_DSP_SLICE_ADDSUB dsp_msb_y
(
.clk (clk),
- .ce_ab1 (1'b0),
- .ce_ab2 (msb_ce),
- .ce_c (msb_ce),
+ .ce_abc (msb_ce),
.ce_p (msb_ce_dly1),
.ce_ctrl (msb_ce),
.ab (msb_ay),
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