[Cryptech-Commits] [core/util/keywrap] 10/37: Updated the keywrap API to support access to MKM status. Updated keywrap_core to support control of MKM access operations.
git at cryptech.is
git at cryptech.is
Wed Apr 29 16:51:46 UTC 2020
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch master
in repository core/util/keywrap.
commit d3e94a0efeec9b2cbac41eea9a57dc3eaf848b21
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Tue Sep 25 14:35:35 2018 +0200
Updated the keywrap API to support access to MKM status. Updated keywrap_core to support control of MKM access operations.
---
src/rtl/keywrap.v | 101 ++++++++++++++++++++++++++++---------------------
src/rtl/keywrap_core.v | 52 +++++++++++++------------
2 files changed, 85 insertions(+), 68 deletions(-)
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 870a85c..829ddd1 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -70,44 +70,47 @@ module keywrap #(parameter ADDR_BITS = 13)
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- localparam ADDR_NAME0 = 8'h00;
- localparam ADDR_NAME1 = 8'h01;
- localparam ADDR_VERSION = 8'h02;
-
- localparam ADDR_CTRL = 8'h08;
- localparam CTRL_INIT_BIT = 0;
- localparam CTRL_NEXT_BIT = 1;
- localparam CTRL_READ_BIT = 2;
- localparam CTRL_WRITE_BIT = 3;
-
- localparam ADDR_STATUS = 8'h09;
- localparam STATUS_READY_BIT = 0;
- localparam STATUS_VALID_BIT = 1;
-
- localparam ADDR_CONFIG = 8'h0a;
- localparam CTRL_ENCDEC_BIT = 0;
- localparam CTRL_KEYLEN_BIT = 1;
-
- localparam ADDR_RLEN = 8'h0c;
- localparam ADDR_A0 = 8'h0e;
- localparam ADDR_A1 = 8'h0f;
-
- localparam ADDR_KEY0 = 8'h10;
- localparam ADDR_KEY1 = 8'h11;
- localparam ADDR_KEY2 = 8'h12;
- localparam ADDR_KEY3 = 8'h13;
- localparam ADDR_KEY4 = 8'h14;
- localparam ADDR_KEY5 = 8'h15;
- localparam ADDR_KEY6 = 8'h16;
- localparam ADDR_KEY7 = 8'h17;
-
- localparam CORE_NAME0 = 32'h6b657920; // "key "
- localparam CORE_NAME1 = 32'h77726170; // "wrap"
- localparam CORE_VERSION = 32'h302e3830; // "0.80"
-
- localparam MEM_BITS = ADDR_BITS - 1;
- localparam RLEN_BITS = ADDR_BITS - 2;
- localparam PAD = ADDR_BITS - 8;
+ localparam ADDR_NAME0 = 8'h00;
+ localparam ADDR_NAME1 = 8'h01;
+ localparam ADDR_VERSION = 8'h02;
+
+ localparam ADDR_CTRL = 8'h08;
+ localparam CTRL_INIT_BIT = 0;
+ localparam CTRL_NEXT_BIT = 1;
+ localparam CTRL_READ_BIT = 2;
+ localparam CTRL_WRITE_BIT = 3;
+
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+
+ localparam ADDR_CONFIG = 8'h0a;
+ localparam CONFIG_ENCDEC_BIT = 0;
+ localparam CONFIG_KEYLEN_BIT = 1;
+ localparam CONFIG_MKS_BIT = 2;
+
+ localparam ADDR_RLEN = 8'h0c;
+ localparam ADDR_A0 = 8'h0e;
+ localparam ADDR_A1 = 8'h0f;
+
+ localparam ADDR_KEY0 = 8'h10;
+ localparam ADDR_KEY1 = 8'h11;
+ localparam ADDR_KEY2 = 8'h12;
+ localparam ADDR_KEY3 = 8'h13;
+ localparam ADDR_KEY4 = 8'h14;
+ localparam ADDR_KEY5 = 8'h15;
+ localparam ADDR_KEY6 = 8'h16;
+ localparam ADDR_KEY7 = 8'h17;
+
+ localparam ADDR_MSTATUS = 8'h20;
+
+ localparam CORE_NAME0 = 32'h6b657920; // "key "
+ localparam CORE_NAME1 = 32'h77726170; // "wrap"
+ localparam CORE_VERSION = 32'h302e3830; // "0.80"
+
+ localparam MEM_BITS = ADDR_BITS - 1;
+ localparam RLEN_BITS = ADDR_BITS - 2;
+ localparam PAD = ADDR_BITS - 8;
// If set to one, will allow read access to key memory.
@@ -130,6 +133,9 @@ module keywrap #(parameter ADDR_BITS = 13)
reg write_reg;
reg write_new;
+ reg mkey_mstatus_reg;
+ reg mkey_mstatus_new;
+
reg encdec_reg;
reg keylen_reg;
reg config_we;
@@ -164,7 +170,8 @@ module keywrap #(parameter ADDR_BITS = 13)
wire core_ready;
wire core_valid;
wire [255 : 0] core_key;
- wire [255 : 0] core_read_key;
+ wire [255 : 0] core_mkey;
+ wire [31 : 0] core_mstatus;
wire [63 : 0] core_a_init;
wire [63 : 0] core_a_result;
wire [31 : 0] core_api_rd_data;
@@ -201,6 +208,7 @@ module keywrap #(parameter ADDR_BITS = 13)
.next(next_reg),
.read(read_reg),
.write(write_reg),
+ .mkey_mstatus(mkey_mstatus_reg),
.encdec(encdec_reg),
.ready(core_ready),
@@ -210,7 +218,8 @@ module keywrap #(parameter ADDR_BITS = 13)
.key(core_key),
.keylen(keylen_reg),
- .read_key(core_read_key),
+ .mkey(core_mkey),
+ .mstatus(core_mstatus),
.a_init(core_a_init),
.a_result(core_a_result),
@@ -238,6 +247,7 @@ module keywrap #(parameter ADDR_BITS = 13)
next_reg <= 1'h0;
read_reg <= 1'h0;
write_reg <= 1'h0;
+ mkey_mstatus_reg <= 1'h0;
encdec_reg <= 1'h0;
keylen_reg <= 1'h0;
rlen_reg <= {RLEN_BITS{1'h0}};
@@ -255,12 +265,14 @@ module keywrap #(parameter ADDR_BITS = 13)
next_reg <= next_new;
read_reg <= read_new;
write_reg <= write_new;
+ mkey_mstatus_reg <= mkey_mstatus_new;
api_rd_delay_reg <= api_rd_delay_new;
if (config_we)
begin
- encdec_reg <= write_data[CTRL_ENCDEC_BIT];
- keylen_reg <= write_data[CTRL_KEYLEN_BIT];
+ mkey_mstatus_reg <= write_data[CONFIG_MKS_BIT];
+ encdec_reg <= write_data[CONFIG_ENCDEC_BIT];
+ keylen_reg <= write_data[CONFIG_KEYLEN_BIT];
end
if (rlen_we)
@@ -364,11 +376,14 @@ module keywrap #(parameter ADDR_BITS = 13)
if (address == {{PAD{1'h0}}, ADDR_A1})
api_rd_delay_new = core_a_result[31 : 0];
+ if (address == {{PAD{1'h0}}, ADDR_MSTATUS})
+ api_rd_delay_new = core_mstatus;
+
// Warning: Should be disabled after mkmif
// integration has been completed.
if (DEBUG_MKM_READ)
if ((address >= {{PAD{1'h0}},ADDR_KEY0}) && (address <= {{PAD{1'h0}}, ADDR_KEY7}))
- api_rd_delay_new = core_read_key[(7 - (address - {{PAD{1'h0}}, ADDR_KEY7})) * 32 +: 32];
+ api_rd_delay_new = core_mkey[(7 - (address - {{PAD{1'h0}}, ADDR_KEY7})) * 32 +: 32];
end // else: !if(we)
end // if (cs)
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 5a05b63..8688e31 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -54,6 +54,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
input wire next,
input wire read,
input wire write,
+ input wire mkey_mstatus,
input wire encdec,
output wire ready,
@@ -63,8 +64,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
input wire [255 : 0] key,
input wire keylen,
- output wire [255 : 0] read_key,
- output wire [31 : 0] mkm_status,
+ output wire [255 : 0] mkey,
+ output wire [31 : 0] mstatus,
input wire [63 : 0] a_init,
output wire [63 : 0] a_result,
@@ -81,21 +82,22 @@ module keywrap_core #(parameter MEM_BITS = 11)
//----------------------------------------------------------------
localparam MAX_ITERATIONS = 6 - 1;
- localparam CTRL_IDLE = 6'h0;
- localparam CTRL_INIT_WAIT = 6'h1;
- localparam CTRL_NEXT_WSTART = 6'h2;
- localparam CTRL_NEXT_USTART = 6'h3;
- localparam CTRL_NEXT_LOOP0 = 6'h4;
- localparam CTRL_NEXT_LOOP = 6'h5;
- localparam CTRL_NEXT_WAIT = 6'h6;
- localparam CTRL_NEXT_UPDATE = 6'h7;
- localparam CTRL_NEXT_WCHECK = 6'h8;
- localparam CTRL_NEXT_UCHECK = 6'h9;
- localparam CTRL_NEXT_FINALIZE = 6'ha;
- localparam CTRL_READ_START = 6'h10;
- localparam CTRL_READ_END = 6'h11;
- localparam CTRL_WRITE_START = 6'h18;
- localparam CTRL_WRITE_END = 6'h19;
+ localparam CTRL_IDLE = 6'h0;
+ localparam CTRL_INIT_WAIT = 6'h1;
+ localparam CTRL_NEXT_WSTART = 6'h2;
+ localparam CTRL_NEXT_USTART = 6'h3;
+ localparam CTRL_NEXT_LOOP0 = 6'h4;
+ localparam CTRL_NEXT_LOOP = 6'h5;
+ localparam CTRL_NEXT_WAIT = 6'h6;
+ localparam CTRL_NEXT_UPDATE = 6'h7;
+ localparam CTRL_NEXT_WCHECK = 6'h8;
+ localparam CTRL_NEXT_UCHECK = 6'h9;
+ localparam CTRL_NEXT_FINALIZE = 6'ha;
+
+ localparam CTRL_MKM_RD_START = 6'h10;
+ localparam CTRL_MKM_RD_END = 6'h11;
+ localparam CTRL_MKM_WR_START = 6'h18;
+ localparam CTRL_MKM_WR_END = 6'h19;
// API for mkm used by the core.
localparam MKM_ADDR_CTRL = 8'h08;
@@ -491,7 +493,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
begin
ready_new = 1'h0;
ready_we = 1'h1;
- keywrap_core_ctrl_new = CTRL_READ_START;
+ keywrap_core_ctrl_new = CTRL_MKM_RD_START;
keywrap_core_ctrl_we = 1'h1;
end
@@ -499,7 +501,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
begin
ready_new = 1'h0;
ready_we = 1'h1;
- keywrap_core_ctrl_new = CTRL_WRITE_START;
+ keywrap_core_ctrl_new = CTRL_MKM_WR_START;
keywrap_core_ctrl_we = 1'h1;
end
end
@@ -633,14 +635,14 @@ module keywrap_core #(parameter MEM_BITS = 11)
end
- CTRL_READ_START:
+ CTRL_MKM_RD_START:
begin
- keywrap_core_ctrl_new = CTRL_READ_END;
+ keywrap_core_ctrl_new = CTRL_MKM_RD_END;
keywrap_core_ctrl_we = 1'h1;
end
- CTRL_READ_END:
+ CTRL_MKM_RD_END:
begin
ready_new = 1'h1;
ready_we = 1'h1;
@@ -649,14 +651,14 @@ module keywrap_core #(parameter MEM_BITS = 11)
end
- CTRL_WRITE_START:
+ CTRL_MKM_WR_START:
begin
- keywrap_core_ctrl_new = CTRL_WRITE_END;
+ keywrap_core_ctrl_new = CTRL_MKM_WR_END;
keywrap_core_ctrl_we = 1'h1;
end
- CTRL_WRITE_END:
+ CTRL_MKM_WR_END:
begin
ready_new = 1'h1;
ready_we = 1'h1;
More information about the Commits
mailing list