[Cryptech-Commits] [user/js/fpga_mkm] branch master updated: Adding registers, control signals and logic for receiving and transmitting bits.

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joachim at secworks.se pushed a commit to branch master
in repository user/js/fpga_mkm.

The following commit(s) were added to refs/heads/master by this push:
     new 4794518  Adding registers, control signals and logic for receiving and transmitting bits.
4794518 is described below

commit 47945186ff63e134ff393e4b433d4b7162a4bbda
Author: Joachim Strömbergson <joachim at assured.se>
AuthorDate: Tue Mar 12 11:34:55 2019 +0100

    Adding registers, control signals and logic for receiving and transmitting bits.
---
 src/rtl/fpga_mkm_spi_slave.v | 87 ++++++++++++++++++++++++++++++++++++--------
 1 file changed, 72 insertions(+), 15 deletions(-)

diff --git a/src/rtl/fpga_mkm_spi_slave.v b/src/rtl/fpga_mkm_spi_slave.v
index 7838b23..473d37d 100644
--- a/src/rtl/fpga_mkm_spi_slave.v
+++ b/src/rtl/fpga_mkm_spi_slave.v
@@ -69,6 +69,7 @@ module fpga_mkm_spi_slave(
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
+  localparam CTRL_IDLE = 3'h0;
 
 
   //----------------------------------------------------------------
@@ -86,32 +87,43 @@ module fpga_mkm_spi_slave(
   reg mosi_sample1_reg;
   reg mosi_reg;
 
-  reg [7 : 0] rx_byte_reg;
+  reg [7 : 0] rx_byte_reg = 8'h0;
   reg [7 : 0] rx_byte_new;
   reg         rx_byte_we;
 
-  reg [2 : 0] rx_bit_ctr_reg;
+  reg [2 : 0] rx_bit_ctr_reg = 3'h0;
   reg [2 : 0] rx_bit_ctr_new;
   reg         rx_bit_ctr_we;
   reg         rx_bit_ctr_rst;
   reg         rx_bit_ctr_inc;
 
-  reg rx_byte_available_reg;
+  reg rx_byte_available_reg = 1'h0;
   reg rx_byte_available_new;
   reg rx_byte_available_we;
 
-  reg [7 : 0] tx_byte_reg;
+  reg [7 : 0] tx_byte_reg = 8'h0;
   reg [7 : 0] tx_byte_new;
   reg         tx_byte_we;
-  reg         tx_byte_set;
-  reg         tx_byte_shift;
+  reg         tx_byte_load;
+  reg         tx_byte_loadz;
+  reg         tx_byte_next;
 
-  reg [2 : 0] tx_bit_ctr_reg;
+  reg [2 : 0] tx_bit_ctr_reg = 3'h0;
   reg [2 : 0] tx_bit_ctr_new;
   reg         tx_bit_ctr_we;
   reg         tx_bit_ctr_rst;
   reg         tx_bit_ctr_inc;
 
+  reg         tx_byte_ack_reg = 1'h0;
+  reg         tx_byte_ack_new;
+
+  reg         tx_byte_error_reg = 1'h0;
+  reg         tx_byte_error_new;
+
+  reg [2 : 0]  spi_slave_ctrl_reg = CTRL_IDLE;
+  reg [2 : 0]  spi_slave_ctrl_new;
+  reg          spi_slave_ctrl_we;
+
 
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
@@ -119,8 +131,8 @@ module fpga_mkm_spi_slave(
   assign miso              = tx_byte_reg[7];
   assign rx_byte_available = rx_byte_available_reg;
   assign rx_byte           = rx_byte_reg;
-  assign tx_byte_ack       = 1'h0;
-  assign tx_byte_error     = 1'h0;
+  assign tx_byte_ack       = tx_byte_ack_reg;
+  assign tx_byte_error     = tx_byte_error_reg;
 
 
   //----------------------------------------------------------------
@@ -140,8 +152,11 @@ module fpga_mkm_spi_slave(
       mosi_sample1_reg <= mosi_sample0_reg;
       mosi_reg         <= mosi_sample1_reg;
 
+      tx_byte_ack_reg <= tx_byte_ack_new;
+      tx_byte_error_reg <= tx_byte_error_new;
+
       if (rx_byte_we)
-        rx_byte_reg <= {rx_byte_reg[], mosi_reg};
+        rx_byte_reg <= {rx_byte_reg[6 : 0], mosi_reg};
 
       if (rx_bit_ctr_we)
         rx_bit_ctr_reg <= rx_bit_ctr_new;
@@ -154,6 +169,39 @@ module fpga_mkm_spi_slave(
 
       if (tx_bit_ctr_we)
         tx_bit_ctr_reg <= tx_bit_ctr_new;
+
+      if (spi_slave_ctrl_we)
+        spi_slave_ctrl_reg <= spi_slave_ctrl_new;
+    end
+
+
+  //----------------------------------------------------------------
+  // tx_byte_logic
+  // Update the tx_byte register. Either loading or shifting to
+  // set the next bit to transmit.
+  //----------------------------------------------------------------
+  always @*
+    begin : tx_byt_logic
+      tx_byte_new = 8'h0;
+      tx_byte_we  = 1'h0;
+
+      if (tx_byte_load)
+        begin
+          tx_byte_new = tx_byte;
+          tx_byte_we  = 1'h1;
+        end
+
+      if (tx_byte_loadz)
+        begin
+          tx_byte_new = 8'h0;
+          tx_byte_we  = 1'h1;
+        end
+
+      if (tx_byte_next)
+        begin
+          tx_byte_new = {tx_byte_reg[6 : 0], 1'h0]};
+          tx_byte_we  = 1'h1;
+        end
     end
 
 
@@ -206,12 +254,21 @@ module fpga_mkm_spi_slave(
   //----------------------------------------------------------------
   always @*
     begin : spi_slave_ctrl_fsm
-      rx_bit_ctr_rst = 1'h0;
-      rx_bit_ctr_inc = 1'h0;
-      tx_bit_ctr_rst = 1'h0;
-      tx_bit_ctr_inc = 1'h0;
-      rx_byte_we     = 1'h0;
+      rx_bit_ctr_rst    = 1'h0;
+      rx_bit_ctr_inc    = 1'h0;
+      tx_bit_ctr_rst    = 1'h0;
+      tx_bit_ctr_inc    = 1'h0;
+      tx_byte_load      = 1'h0;
+      tx_byte_loadz     = 1'h0;
+      tx_byte_next      = 1'h0;
+      tx_byte_ack_new   = 1'h0;
+      tx_byte_error_new = 1'h0;
+      rx_byte_we        = 1'h0;
+
+
+      case (spi_slave_ctrl_reg)
 
+      endcase // case (spi_slave_ctrl_reg)
     end
 
 endmodule // fpga_mkm_spi_slave

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