[Cryptech-Commits] [user/js/keywrap] branch master updated: Increased size of memory to 64 kByte to match what is needed for key wrap. No problems.
git at cryptech.is
git at cryptech.is
Thu Jun 21 21:16:16 UTC 2018
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joachim at secworks.se pushed a commit to branch master
in repository user/js/keywrap.
The following commit(s) were added to refs/heads/master by this push:
new a472f7e Increased size of memory to 64 kByte to match what is needed for key wrap. No problems.
a472f7e is described below
commit a472f7ea100df42250f8628fa4c02c122f179f81
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Thu Jun 21 23:16:02 2018 +0200
Increased size of memory to 64 kByte to match what is needed for key wrap. No problems.
---
src/rtl/keywrap_mem.v | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index a9e80d8..8ddb465 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -44,12 +44,12 @@ module keywrap_mem
input wire reset_n,
input wire api_we,
- input wire [8 : 0] api_addr,
+ input wire [13 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire core_we,
- input wire [7 : 0] core_addr,
+ input wire [12 : 0] core_addr,
input wire [63 : 0] core_wr_data,
output wire [63 : 0] core_rd_data
);
@@ -65,14 +65,14 @@ module keywrap_mem
reg [31 : 0] tmp_core_rd_data0;
reg [31 : 0] tmp_core_rd_data1;
- reg [31 : 0] mem0 [0 : 255];
+ reg [31 : 0] mem0 [0 : 8191];
reg [31 : 0] mem0_data;
- reg [7 : 0] mem0_addr;
+ reg [12 : 0] mem0_addr;
reg mem0_we;
- reg [31 : 0] mem1 [0 : 255];
+ reg [31 : 0] mem1 [0 : 8191];
reg [31 : 0] mem1_data;
- reg [7 : 0] mem1_addr;
+ reg [12 : 0] mem1_addr;
reg mem1_we;
@@ -89,7 +89,7 @@ module keywrap_mem
always @(posedge clk)
begin : mem0_access
tmp_core_rd_data0 <= mem0[core_addr];
- tmp_api_rd_data0 <= mem0[api_addr[8 : 1]];
+ tmp_api_rd_data0 <= mem0[api_addr[13 : 1]];
if (mem0_we)
mem0[mem0_addr] <= mem0_data;
@@ -102,13 +102,15 @@ module keywrap_mem
always @(posedge clk)
begin : mem1_access
tmp_core_rd_data1 <= mem1[core_addr];
- tmp_api_rd_data1 <= mem1[api_addr[8 : 1]];
+ tmp_api_rd_data1 <= mem1[api_addr[13 : 1]];
if (mem1_we)
mem1[mem1_addr] <= mem1_data;
end
+ //----------------------------------------------------------------
+ //----------------------------------------------------------------
always @*
begin
if (api_addr[0])
@@ -144,18 +146,15 @@ module keywrap_mem
else if (api_we)
begin
+ mem0_addr = api_addr[13 : 1];
+ mem0_data = api_wr_data;
+ mem1_addr = api_addr[13 : 1];
+ mem1_data = api_wr_data;
+
if (api_addr[0])
- begin
- mem1_data = api_wr_data;
- mem1_addr = api_addr[7 : 0];
- mem1_we = 1'h1;
- end
+ mem1_we = 1'h1;
else
- begin
- mem0_data = api_wr_data;
- mem0_addr = api_addr[7 : 0];
- mem0_we = 1'h1;
- end
+ mem0_we = 1'h1;
end
end
endmodule // keywrap_mem
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