[Cryptech-Commits] [core/platform/alpha] 01/01: correct fpga part number, add keywrap build target

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch js_keywrap
in repository core/platform/alpha.

commit 7be8f9437441b07793e3b0f2a220cb15cc206354
Author: Paul Selkirk <paul at psgd.org>
AuthorDate: Mon Aug 27 16:59:34 2018 -0400

    correct fpga part number, add keywrap build target
---
 build/Makefile | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/build/Makefile b/build/Makefile
index 4e3a9bb..8115637 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -12,7 +12,7 @@ WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0))
 project		?= alpha_fmc
 vendor		= xilinx
 family		= artix7
-part		= xc7a200tfbg484-3
+part		= xc7a200tfbg484-1
 top_module	= alpha_fmc_top
 isedir		= /opt/Xilinx/14.7/ISE_DS
 xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
@@ -60,6 +60,10 @@ hsm-super:
 	$(CONFIG_GEN) -p hsm-super
 	$(MAKE) project=$(project)_hsm-super ucf=$(ucf)
 
+keywrap:
+	$(CONFIG_GEN) -p keywrap
+	$(MAKE) project=$(project)_keywrap ucf=$(ucf)
+
 # Verilog files that always go with builds on this platform.
 
 vfiles = \