[Cryptech-Commits] [core/cipher/chacha] branch timing_fix updated: (1) Updated qr interface to include clock and reset needed for internal pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support.
git at cryptech.is
git at cryptech.is
Thu Aug 23 07:53:39 UTC 2018
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joachim at secworks.se pushed a commit to branch timing_fix
in repository core/cipher/chacha.
The following commit(s) were added to refs/heads/timing_fix by this push:
new 1721ef5 (1) Updated qr interface to include clock and reset needed for internal pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support.
1721ef5 is described below
commit 1721ef5b165aee52554675f6ceb1e3a1fc2fb031
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Thu Aug 23 09:53:03 2018 +0200
(1) Updated qr interface to include clock and reset needed for internal pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support.
---
src/rtl/chacha_core.v | 12 +++
src/rtl/chacha_qr.v | 29 +++++++
src/tb/tb_chacha_qr.v | 213 ++++++++++++++++++++++++++++++++++++++++++++++++++
toolruns/Makefile | 54 +++++++++----
4 files changed, 292 insertions(+), 16 deletions(-)
diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v
index 5f496a4..d68f783 100644
--- a/src/rtl/chacha_core.v
+++ b/src/rtl/chacha_core.v
@@ -191,6 +191,9 @@ module chacha_core(
// Instantiation of the qr modules.
//----------------------------------------------------------------
chacha_qr qr0(
+ .clk(clk),
+ .reset_n(reset_n),
+
.a(qr0_a),
.b(qr0_b),
.c(qr0_c),
@@ -203,6 +206,9 @@ module chacha_core(
);
chacha_qr qr1(
+ .clk(clk),
+ .reset_n(reset_n),
+
.a(qr1_a),
.b(qr1_b),
.c(qr1_c),
@@ -215,6 +221,9 @@ module chacha_core(
);
chacha_qr qr2(
+ .clk(clk),
+ .reset_n(reset_n),
+
.a(qr2_a),
.b(qr2_b),
.c(qr2_c),
@@ -227,6 +236,9 @@ module chacha_core(
);
chacha_qr qr3(
+ .clk(clk),
+ .reset_n(reset_n),
+
.a(qr3_a),
.b(qr3_b),
.c(qr3_c),
diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v
index 42e644c..e1ddbd8 100644
--- a/src/rtl/chacha_qr.v
+++ b/src/rtl/chacha_qr.v
@@ -40,6 +40,9 @@
//======================================================================
module chacha_qr(
+ input wire clk,
+ input wire reset_n,
+
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
@@ -51,6 +54,13 @@ module chacha_qr(
output wire [31 : 0] d_prim
);
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg [31 : 0] a0_reg;
+ reg [31 : 0] a0_new;
+
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
@@ -69,6 +79,23 @@ module chacha_qr(
assign d_prim = internal_d_prim;
+ //----------------------------------------------------------------
+ // reg_update
+ //----------------------------------------------------------------
+ always @ (posedge clk)
+ begin : reg_update
+ if (!reset_n)
+ begin
+ a0_reg <= 32'h0;
+ end
+
+ else
+ begin
+ a0_reg <= a0_new;
+ end
+ end // reg_update
+
+
//----------------------------------------------------------------
// qr
//
@@ -93,6 +120,8 @@ module chacha_qr(
reg [31 : 0] d3;
a0 = a + b;
+ a0_new = a + b;
+
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
diff --git a/src/tb/tb_chacha_qr.v b/src/tb/tb_chacha_qr.v
new file mode 100644
index 0000000..66a790c
--- /dev/null
+++ b/src/tb/tb_chacha_qr.v
@@ -0,0 +1,213 @@
+//======================================================================
+//
+// tb_chacha_qr.v
+// --------------
+// Testbench for the Chacha stream cipher quarerround (QR) module.
+//
+//
+// Author: Joachim Strombergson
+// Copyright (c) 2018, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module tb_chacha_qr();
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter CLK_HALF_PERIOD = 2;
+ parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+
+
+ //----------------------------------------------------------------
+ // Register and Wire declarations.
+ //----------------------------------------------------------------
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg tb_clk;
+ reg tb_reset_n;
+
+ reg [31 : 0] a;
+ reg [31 : 0] b;
+ reg [31 : 0] c;
+ reg [31 : 0] d;
+
+ wire [31 : 0] a_prim;
+ wire [31 : 0] b_prim;
+ wire [31 : 0] c_prim;
+ wire [31 : 0] d_prim;
+
+ reg display_cycle_ctr;
+ reg display_ctrl_and_ctrs;
+ reg display_qround;
+ reg display_state;
+
+
+ //----------------------------------------------------------------
+ // chacha_core device under test.
+ //----------------------------------------------------------------
+ chacha_qr dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .a(a),
+ .b(b),
+ .c(c),
+ .d(d),
+
+ .a_prim(a_prim),
+ .b_prim(b_prim),
+ .c_prim(c_prim),
+ .d_prim(d_prim)
+ );
+
+
+ //----------------------------------------------------------------
+ // clk_gen
+ //
+ // Clock generator process.
+ //----------------------------------------------------------------
+ always
+ begin : clk_gen
+ #CLK_HALF_PERIOD tb_clk = !tb_clk;
+ end // clk_gen
+
+
+ //--------------------------------------------------------------------
+ // dut_monitor
+ //
+ // Monitor that displays different types of information
+ // every cycle depending on what flags test cases enable.
+ //
+ // The monitor includes a cycle counter for the testbench.
+ //--------------------------------------------------------------------
+ always @ (posedge tb_clk)
+ begin : dut_monitor
+ cycle_ctr = cycle_ctr + 1;
+
+ $display("cycle = %08x:", cycle_ctr);
+ $display("");
+
+ $display("a = %08x, b = %08x, c = %08x, d = %08x",
+ a, b, c, d);
+ $display("a_prim = %08x, b_prim = %08x, c_prim = %08x, d_prim = %08x",
+ a_prim, b_prim, c_prim, d_prim);
+ $display("");
+ end // dut_monitor
+
+
+ //----------------------------------------------------------------
+ // cycle_reset()
+ //
+ // Cycles the reset signal on the dut.
+ //----------------------------------------------------------------
+ task cycle_reset;
+ begin
+ tb_reset_n = 0;
+ #(CLK_PERIOD);
+
+ @(negedge tb_clk)
+
+ tb_reset_n = 1;
+ #(CLK_PERIOD);
+ end
+ endtask // cycle_reset
+
+
+ //----------------------------------------------------------------
+ // init_sim()
+ //
+ // Set the input to the DUT to defined values.
+ //----------------------------------------------------------------
+ task init_sim;
+ begin
+ cycle_ctr = 0;
+ tb_clk = 0;
+ tb_reset_n = 0;
+ error_ctr = 0;
+ end
+ endtask // init_dut
+
+
+ //----------------------------------------------------------------
+ // qr_tests()
+ //
+ // Run some simple test on the qr logic.
+ // Note: Not self testing. No expected value used.
+ //----------------------------------------------------------------
+ task qr_tests;
+ begin
+ $display("*** Test of Quarterround:");
+ $display("");
+ a = 32'h11223344;
+ b = 32'h11223344;
+ c = 32'h11223344;
+ d = 32'h11223344;
+
+ #(CLK_PERIOD * 10);
+
+ a = 32'h55555555;
+ b = 32'h55555555;
+ c = 32'h55555555;
+ d = 32'h55555555;
+
+ #(CLK_PERIOD * 10);
+ end
+ endtask // qr_tests
+
+
+ //----------------------------------------------------------------
+ // chacha_qr_test
+ //
+ // The main test functionality.
+ //----------------------------------------------------------------
+ initial
+ begin : chacha_qr_test
+ $display(" -- Testbench for chacha qr started --");
+ $display("");
+
+ init_sim();
+ #(CLK_PERIOD * 10);
+ cycle_reset();
+ #(CLK_PERIOD * 10);
+
+ qr_tests();
+
+ // Finish in style.
+ $display(" -- Testbench for chacha qr completed --");
+ $finish;
+ end // chacha_core_test
+
+endmodule // tb_chacha_qr
+
+//======================================================================
+// EOF tb_chacha_qr.v
+//======================================================================
diff --git a/toolruns/Makefile b/toolruns/Makefile
index 6f94769..d8e6ad3 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -36,49 +36,71 @@
#
#===================================================================
-CORE_SRC=../src/rtl/chacha_core.v ../src/rtl/chacha_qr.v
-CORE_TB_SRC=../src/tb/tb_chacha_core.v
+QR_SRC = ../src/rtl/chacha_qr.v
+QR_TB_SRC = ../src/tb/tb_chacha_qr.v
-TOP_SRC=../src/rtl/chacha.v $(CORE_SRC)
-TOP_TB_SRC=../src/tb/tb_chacha.v
+CORE_SRC = ../src/rtl/chacha_core.v $(QR_SRC)
+CORE_TB_SRC = ../src/tb/tb_chacha_core.v
-CC=iverilog
+TOP_SRC = ../src/rtl/chacha.v $(CORE_SRC)
+TOP_TB_SRC = ../src/tb/tb_chacha.v
+CC = iverilog
+CC_FLAGS = -Wall
-all: top core
+LINT = verilator
+LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
+
+
+all: top core qr
top: $(TOP_TB_SRC) $(TOP_SRC)
- $(CC) -o top.sim $(TOP_TB_SRC) $(TOP_SRC)
+ $(CC) $(CC_FLAGS) -o top.sim $(TOP_TB_SRC) $(TOP_SRC)
core: $(CORE_TB_SRC) $(CORE_SRC)
- $(CC) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
+ $(CC) $(CC_FLAGS) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
-sim-core: core.sim
- ./core.sim
+qr: $(QR_TB_SRC) $(QR_SRC)
+ $(CC) $(CC_FLAGS) -o qr.sim $(QR_SRC) $(QR_TB_SRC)
-sim-top: top.sim
+sim-top: top
./top.sim
+sim-core: core
+ ./core.sim
+
+
+sim-qr: qr
+ ./qr.sim
+
+
+lint: $(TOP_SRC)
+ $(LINT) $(LINT_FLAGS) $(TOP_SRC)
+
+
help:
@echo "Supported targets:"
@echo "------------------"
@echo "all: Build all simulation targets."
@echo "top: Build the top simulation target."
- @echo "core: Build the top simulation target."
- @echo "sim-top: Run top level simulation."
- @echo "sim-core: Run core level simulation."
+ @echo "core: Build the core simulation target."
+ @echo "qr : Build the qr simulation target."
+ @echo "sim-top: Run top simulation."
+ @echo "sim-core: Run core simulation."
+ @echo "sim-qr: Run qr simulation."
+ @echo "lint: Lint the design."
@echo "debug: Print the internal varibles."
clean:
- rm -f core.sim
rm -f top.sim
+ rm -f core.sim
+ rm -f qr.sim
#===================================================================
# EOF Makefile
#===================================================================
-
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