[Cryptech-Commits] [core/hash/sha1] branch master updated: Removed redundant FSM from the W memory.
git at cryptech.is
git at cryptech.is
Fri Apr 27 08:11:57 UTC 2018
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joachim at secworks.se pushed a commit to branch master
in repository core/hash/sha1.
The following commit(s) were added to refs/heads/master by this push:
new 44ef1a5 Removed redundant FSM from the W memory.
44ef1a5 is described below
commit 44ef1a541c44b0f47a73ac106d208cf3e4f5e132
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Apr 27 10:11:46 2018 +0200
Removed redundant FSM from the W memory.
---
src/rtl/sha1_w_mem.v | 71 +++++++-------------------------------------------
src/tb/tb_sha1_w_mem.v | 4 +--
2 files changed, 11 insertions(+), 64 deletions(-)
diff --git a/src/rtl/sha1_w_mem.v b/src/rtl/sha1_w_mem.v
index f50741e..2ba80f5 100644
--- a/src/rtl/sha1_w_mem.v
+++ b/src/rtl/sha1_w_mem.v
@@ -86,12 +86,6 @@ module sha1_w_mem(
reg [6 : 0] w_ctr_reg;
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
- reg w_ctr_inc;
- reg w_ctr_rst;
-
- reg sha1_w_mem_ctrl_reg;
- reg sha1_w_mem_ctrl_new;
- reg sha1_w_mem_ctrl_we;
//----------------------------------------------------------------
@@ -123,7 +117,7 @@ module sha1_w_mem(
for (i = 0 ; i < 16 ; i = i + 1)
w_mem[i] <= 32'h0;
- sha1_w_mem_ctrl_reg <= CTRL_IDLE;
+ w_ctr_reg <= 7'h0;
end
else
begin
@@ -149,9 +143,6 @@ module sha1_w_mem(
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
-
- if (sha1_w_mem_ctrl_we)
- sha1_w_mem_ctrl_reg <= sha1_w_mem_ctrl_new;
end
end // reg_update
@@ -165,13 +156,9 @@ module sha1_w_mem(
always @*
begin : select_w
if (w_ctr_reg < 16)
- begin
- w_tmp = w_mem[w_ctr_reg[3 : 0]];
- end
+ w_tmp = w_mem[w_ctr_reg[3 : 0]];
else
- begin
- w_tmp = w_new;
- end
+ w_tmp = w_new;
end // select_w
@@ -235,7 +222,7 @@ module sha1_w_mem(
w_mem_we = 1;
end
- else if (w_ctr_reg > 15)
+ if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
@@ -267,60 +254,20 @@ module sha1_w_mem(
always @*
begin : w_ctr
w_ctr_new = 7'h0;
- w_ctr_we = 0;
+ w_ctr_we = 1'h0;
- if (w_ctr_rst)
+ if (init)
begin
w_ctr_new = 7'h0;
- w_ctr_we = 1;
+ w_ctr_we = 1'h1;
end
- if (w_ctr_inc)
+ if (next)
begin
w_ctr_new = w_ctr_reg + 7'h01;
- w_ctr_we = 1;
+ w_ctr_we = 1'h1;
end
end // w_ctr
-
-
- //----------------------------------------------------------------
- // sha1_w_mem_fsm
- //
- // Logic for the w shedule FSM.
- //----------------------------------------------------------------
- always @*
- begin : sha1_w_mem_fsm
- w_ctr_rst = 0;
- w_ctr_inc = 0;
- sha1_w_mem_ctrl_new = CTRL_IDLE;
- sha1_w_mem_ctrl_we = 0;
-
- case (sha1_w_mem_ctrl_reg)
- CTRL_IDLE:
- begin
- if (init)
- begin
- w_ctr_rst = 1;
- sha1_w_mem_ctrl_new = CTRL_UPDATE;
- sha1_w_mem_ctrl_we = 1;
- end
- end
-
- CTRL_UPDATE:
- begin
- if (next)
- begin
- w_ctr_inc = 1;
- end
-
- if (w_ctr_reg == SHA1_ROUNDS)
- begin
- sha1_w_mem_ctrl_new = CTRL_IDLE;
- sha1_w_mem_ctrl_we = 1;
- end
- end
- endcase // case (sha1_ctrl_reg)
- end // sha1_w_mem_fsm
endmodule // sha1_w_mem
//======================================================================
diff --git a/src/tb/tb_sha1_w_mem.v b/src/tb/tb_sha1_w_mem.v
index 1ee018f..2d19525 100644
--- a/src/tb/tb_sha1_w_mem.v
+++ b/src/tb/tb_sha1_w_mem.v
@@ -128,8 +128,8 @@ module tb_sha1_w_mem();
$display("W state:");
- $display("ctrl_reg = %01x, w_ctr_reg = %02x, init = %01x, next = %01x",
- dut.sha1_w_mem_ctrl_reg, dut.w_ctr_reg, dut.init, dut.next);
+ $display("w_ctr_reg = %02x, init = %01x, next = %01x",
+ dut.w_ctr_reg, dut.init, dut.next);
$display("w_tmp = %08x, w_new = %08x", dut.w_tmp, dut.w_new);
--
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