[Cryptech-Commits] [user/ft/alpha_to_kicad] 02/03: tune clearances
git at cryptech.is
git at cryptech.is
Mon Apr 23 15:14:58 UTC 2018
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fredrik at thulin.net pushed a commit to branch master
in repository user/ft/alpha_to_kicad.
commit 0c02172f9bab43730b5a22fef8aa5265ab649675
Author: Fredrik Thulin <fredrik at thulin.net>
AuthorDate: Mon Apr 23 17:11:37 2018 +0200
tune clearances
---
fix-pcb.py | 52 ++++++++++++++++++++++++++++------
rev03-KiCad/Cryptech Alpha.kicad_pcb | 55 ++++++++++++++++--------------------
2 files changed, 69 insertions(+), 38 deletions(-)
diff --git a/fix-pcb.py b/fix-pcb.py
index 83f0136..52dc67f 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -46,7 +46,7 @@ def hide_layers_except(board, layers):
board.SetVisibleLayers(visible_set)
-def layer_zone_fixes(board, layer, clearance=0.15, min_width=0.05, thermal=0.5,
+def layer_zone_fixes(board, layer, clearance=0.125, min_width=0.05, thermal=0.5,
gnd_clearance=0.25, gnd_min_width=0.05, gnd_thermal=0.5, gnd_priority=50):
for i in range(board.GetAreaCount()):
area = board.GetArea(i)
@@ -80,19 +80,36 @@ def change_via_drill_size(board, from_size, to_drill):
Oddly enough, these have a 'width' of 1000000 but need to have the drill size set
to not inherit the default for the net class which will be 0.25 mm.
"""
- sizes = {}
from_size = pcbnew.FromMM(from_size)
for this in board.GetTracks():
if type(this) is pcbnew.VIA:
size = this.GetWidth()
- sizes[size] = sizes.get(size, 0) + 1
if size == from_size:
this.SetDrill(pcbnew.FromMM(to_drill))
- #else:
- # help(this)
- # print('Not changing drill {} to {}'.format(this.GetDrill(), to_drill))
+
+def change_via_width(board, from_, to_):
+ """
+ """
+ changed = 0
+ from_ = pcbnew.FromMM(from_)
+ for this in board.GetTracks():
+ if type(this) is pcbnew.VIA:
+ size = this.GetWidth()
+ if size == from_:
+ this.SetWidth(pcbnew.FromMM(to_))
+ changed += 1
+ print("Changed {} via's from width {} to {}".format(changed, from_, to_))
+
+
+def show_via_widths(board):
+ sizes = {}
+ for this in board.GetTracks():
+ if type(this) is pcbnew.VIA:
+ size = this.GetWidth()
+ sizes[size] = sizes.get(size, 0) + 1
print("Via 'widths': {}".format(sizes))
+
def change_netclass_drill_size(board, from_, to_):
#help(board.GetDesignSettings())
names = board.GetAllNetClasses()
@@ -102,6 +119,14 @@ def change_netclass_drill_size(board, from_, to_):
net.SetViaDrill(pcbnew.FromMM(to_))
+def change_netclass_clearance(board, to_):
+ names = board.GetAllNetClasses()
+ for name, net in names.iterator():
+ old = net.GetClearance()
+ print("Netclass {} has clearance {}, changing to {}".format(name, pcbnew.ToMM(old), pcbnew.FromMM(to_)))
+ net.SetClearance(pcbnew.FromMM(to_))
+
+
#
# One function per layer
#
@@ -134,7 +159,7 @@ def fix_layer_In1_aka_GP1(board):
$ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In1.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP1
"""
- layer_zone_fixes(board, 'In1.Cu', gnd_clearance=0.15)
+ layer_zone_fixes(board, 'In1.Cu', gnd_clearance=0.125)
def fix_layer_In2_aka_G1(board):
@@ -164,7 +189,6 @@ def fix_layer_In3_aka_GP2(board):
def fix_layer_In4_aka_GP3(board):
"""
-
Layer 4 is a layer with large polygons (GND and Power). In Altium, this was made
like an inverted layer with drawn lines separating polygons. Issues were with
line thickness in Kicad, clearance parameters preventing copper to flow in between
@@ -176,6 +200,11 @@ def fix_layer_In4_aka_GP3(board):
$ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In4.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.GP3
"""
remove_tracks(board, 'In4.Cu')
+ # GND clearance should be 0.125 to minimise diff around thoughholes in the GND polygon
+ # (best seen around the SDRAM vias on the right hand side), but that also makes the
+ # line separating the polygons thinner, so I'll keep it this way. Maybe these polygons
+ # should get a manual touch-up after conversion anyways - the isolated GND polygon in
+ # the middle has a bit of an odd shape.
layer_zone_fixes(board, 'In4.Cu', gnd_clearance=0.25)
@@ -244,7 +273,14 @@ def main(in_fn='rev03-KiCad/convert.kicad_pcb', out_fn='rev03-KiCad/Cryptech Alp
fix_layer_B_aka_GBL(board)
change_via_drill_size(board, 1.0, 0.5)
+ # Changing these via widths minimizes diff on layer In1/GP1, but creates diff on
+ # the top layer. Altium seems to have different internal layer clearings than KiCAD.
+ #change_via_width(board, 0.5, 0.45)
+ #change_via_width(board, 1.0, 0.7)
+ #change_via_width(board, 1.5, 1.2)
+ show_via_widths(board)
change_netclass_drill_size(board, 0.635, 0.250)
+ change_netclass_clearance(board, 0.125)
# Only show a single layer while working on this
#hide_layers_except(board, ['In5.Cu'])
diff --git a/rev03-KiCad/Cryptech Alpha.kicad_pcb b/rev03-KiCad/Cryptech Alpha.kicad_pcb
index 47d0359..155ef73 100644
--- a/rev03-KiCad/Cryptech Alpha.kicad_pcb
+++ b/rev03-KiCad/Cryptech Alpha.kicad_pcb
@@ -3,7 +3,7 @@
(general
(thickness 1.6)
(drawings 6665)
- (tracks 9210)
+ (tracks 9205)
(zones 0)
(modules 386)
(nets 304)
@@ -41,7 +41,7 @@
(setup
(last_trace_width 0.254)
- (trace_clearance 0.15)
+ (trace_clearance 0.125)
(zone_clearance 0.0144)
(zone_45_only no)
(trace_min 0.15)
@@ -401,7 +401,7 @@
(net 303 VCCO_3V3)
(net_class Default "This is the default net class."
- (clearance 0.15)
+ (clearance 0.125)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.25)
@@ -613,7 +613,7 @@
)
(net_class Default "This is the default net class."
- (clearance 0.15)
+ (clearance 0.125)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.25)
@@ -825,7 +825,7 @@
)
(net_class FMC FMC
- (clearance 0.15)
+ (clearance 0.125)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.25)
@@ -910,7 +910,7 @@
)
(net_class FPGA_GPIO FPGA_GPIO
- (clearance 0.15)
+ (clearance 0.125)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.25)
@@ -935,7 +935,7 @@
)
(net_class USB USB
- (clearance 0.15)
+ (clearance 0.125)
(trace_width 0.254)
(via_dia 0.889)
(via_drill 0.25)
@@ -23115,11 +23115,6 @@
(segment (start 91.775 -65.625) (end 92.83933 -64.56067) (width 0.15) (layer F.Cu) (net 161))
(segment (start 82.925 -65.625) (end 91.775 -65.625) (width 0.15) (layer F.Cu) (net 161))
(segment (start 93.59713 -64.56067) (end 94.8102 -63.3476) (width 0.15) (layer F.Cu) (net 161))
- (segment (start 10.1253 -31) (end 11.35 -32.2247) (width 0.15) (layer F.Cu) (net 1))
- (segment (start 11.35 -32.2247) (end 11.35 -32.8253) (width 0.15) (layer F.Cu) (net 1))
- (segment (start 9.3497 -31) (end 10.1253 -31) (width 0.15) (layer F.Cu) (net 1))
- (segment (start 9.05477 -31.29493) (end 9.3497 -31) (width 0.15) (layer F.Cu) (net 1))
- (segment (start 6.75523 -31.29493) (end 9.05477 -31.29493) (width 0.15) (layer F.Cu) (net 1))
(segment (start 10.625 -32.525) (end 10.625 -33.6) (width 0.5) (layer F.Cu) (net 303))
(segment (start 68.55 -55.85) (end 68.55 -57.175) (width 1) (layer F.Cu) (net 303))
(segment (start 89.72163 -4.9) (end 93.1 -4.9) (width 0.15) (layer F.Cu) (net 182))
@@ -29762,7 +29757,7 @@
(zone (net 237) (net_name NetC117_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 47)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29776,7 +29771,7 @@
)
(zone (net 284) (net_name PWR_18V) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 65)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29802,7 +29797,7 @@
)
(zone (net 242) (net_name NetC208_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 59)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29814,7 +29809,7 @@
)
(zone (net 175) (net_name FPGA_VCCAUX_1V8) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 58)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29826,7 +29821,7 @@
)
(zone (net 176) (net_name FPGA_VCCINT_1V0) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 56)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29877,7 +29872,7 @@
)
(zone (net 239) (net_name NetC118_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 50)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29890,7 +29885,7 @@
)
(zone (net 302) (net_name VCC_5V0) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 60)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -29989,7 +29984,7 @@
)
(zone (net 175) (net_name FPGA_VCCAUX_1V8) (layer F.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 53)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30040,7 +30035,7 @@
)
(zone (net 284) (net_name PWR_18V) (layer In2.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 46)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30053,7 +30048,7 @@
)
(zone (net 284) (net_name PWR_18V) (layer In5.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 45)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30080,7 +30075,7 @@
)
(zone (net 7) (net_name GND) (layer In1.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 50)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30098,7 +30093,7 @@
)
(zone (net 303) (net_name VCCO_3V3) (layer In3.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30116,7 +30111,7 @@
)
(zone (net 176) (net_name FPGA_VCCINT_1V0) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30141,7 +30136,7 @@
)
(zone (net 175) (net_name FPGA_VCCAUX_1V8) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30181,7 +30176,7 @@
)
(zone (net 186) (net_name FT_MGMT_VCC3V3) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30200,7 +30195,7 @@
)
(zone (net 284) (net_name PWR_18V) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30217,7 +30212,7 @@
)
(zone (net 199) (net_name FT_VCC3V3) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
@@ -30266,7 +30261,7 @@
)
(zone (net 4) (net_name 3V3_BATT) (layer In4.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
(priority 100)
- (connect_pads thru_hole_only (clearance 0.15))
+ (connect_pads thru_hole_only (clearance 0.125))
(min_thickness 0.05)
(fill (mode segment) (arc_segments 32) (thermal_gap 0.254) (thermal_bridge_width 0.5))
(polygon
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