[Cryptech-Commits] [core/hash/sha512] 02/03: Added registers for t1 and t2. Updated tb to look at update vectors.

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joachim at secworks.se pushed a commit to branch clock_speed
in repository core/hash/sha512.

commit 4c777a27705f6d87b7b8cd0f5c312b9023ebb662
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Apr 6 14:07:57 2018 +0200

    Added registers for t1 and t2. Updated tb to look at update vectors.
---
 src/rtl/sha512_core.v   | 67 ++++++++++++++++++++++++++++---------------------
 src/tb/tb_sha512_core.v |  6 ++---
 2 files changed, 42 insertions(+), 31 deletions(-)

diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index 1b1aeda..576d872 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -108,6 +108,13 @@ module sha512_core(
   reg [63 : 0] h_new;
   reg          a_h_we;
 
+  reg [63 : 0] t1_reg;
+  reg [63 : 0] t1_new;
+  reg          t1_we;
+  reg [63 : 0] t2_reg;
+  reg [63 : 0] t2_new;
+  reg          t2_we;
+
   reg [63 : 0] H0_reg;
   reg [63 : 0] H0_new;
   reg [63 : 0] H1_reg;
@@ -147,7 +154,6 @@ module sha512_core(
   reg [1 : 0] sha512_ctrl_new;
   reg         sha512_ctrl_we;
 
-  reg [63 : 0] t1_reg;
 
   //----------------------------------------------------------------
   // Wires.
@@ -162,9 +168,6 @@ module sha512_core(
 
   reg ready_flag;
 
-  reg [63 : 0] t1;
-  reg [63 : 0] t2;
-
   wire [63 : 0] k_data;
 
   reg           w_init;
@@ -237,31 +240,36 @@ module sha512_core(
     begin : reg_update
       if (!reset_n)
         begin
-          a_reg               <= 64'h0000000000000000;
-          b_reg               <= 64'h0000000000000000;
-          c_reg               <= 64'h0000000000000000;
-          d_reg               <= 64'h0000000000000000;
-          e_reg               <= 64'h0000000000000000;
-          f_reg               <= 64'h0000000000000000;
-          g_reg               <= 64'h0000000000000000;
-          h_reg               <= 64'h0000000000000000;
-          H0_reg              <= 64'h0000000000000000;
-          H1_reg              <= 64'h0000000000000000;
-          H2_reg              <= 64'h0000000000000000;
-          H3_reg              <= 64'h0000000000000000;
-          H4_reg              <= 64'h0000000000000000;
-          H5_reg              <= 64'h0000000000000000;
-          H6_reg              <= 64'h0000000000000000;
-          H7_reg              <= 64'h0000000000000000;
-          work_factor_ctr_reg <= 32'h00000000;
-          digest_valid_reg    <= 0;
+          a_reg               <= 64'h0;
+          b_reg               <= 64'h0;
+          c_reg               <= 64'h0;
+          d_reg               <= 64'h0;
+          e_reg               <= 64'h0;
+          f_reg               <= 64'h0;
+          g_reg               <= 64'h0;
+          h_reg               <= 64'h0;
+          t1_reg              <= 64'h0;
+          t2_reg              <= 64'h0;
+          H0_reg              <= 64'h0;
+          H1_reg              <= 64'h0;
+          H2_reg              <= 64'h0;
+          H3_reg              <= 64'h0;
+          H4_reg              <= 64'h0;
+          H5_reg              <= 64'h0;
+          H6_reg              <= 64'h0;
+          H7_reg              <= 64'h0;
+          work_factor_ctr_reg <= 32'h0;
+          digest_valid_reg    <= 1'h0;
           round_ctr_reg       <= 7'h0;
           sha512_ctrl_reg     <= CTRL_IDLE;
-          t1_reg              <= 64'h0;
         end
       else
         begin
-          t1_reg <= t1;
+          if (t1_we)
+            t1_reg <= t1_new;
+
+          if (t2_we)
+            t2_reg <= t2_new;
 
           if (a_h_we)
             begin
@@ -419,7 +427,7 @@ module sha512_core(
 
       ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
 
-      t1 = h_reg + sum1 + ch + k_data + w_data;
+      t1_new = h_reg + sum1 + ch + k_data + w_data;
     end // t1_logic
 
 
@@ -439,7 +447,7 @@ module sha512_core(
 
       maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
 
-      t2 = sum0 + maj;
+      t2_new = sum0 + maj;
     end // t2_logic
 
 
@@ -491,11 +499,11 @@ module sha512_core(
 
       if (state_update)
         begin
-          a_new  = t1 + t2;
+          a_new  = t1_new + t2_new;
           b_new  = a_reg;
           c_new  = b_reg;
           d_new  = c_reg;
-          e_new  = d_reg + t1;
+          e_new  = d_reg + t1_new;
           f_new  = e_reg;
           g_new  = f_reg;
           h_new  = g_reg;
@@ -571,6 +579,9 @@ module sha512_core(
       state_init          = 0;
       state_update        = 0;
 
+      t1_we               = 1;
+      t2_we               = 1;
+
       first_block         = 0;
       ready_flag          = 0;
 
diff --git a/src/tb/tb_sha512_core.v b/src/tb/tb_sha512_core.v
index 955fee6..0d198d6 100644
--- a/src/tb/tb_sha512_core.v
+++ b/src/tb/tb_sha512_core.v
@@ -176,7 +176,7 @@ module tb_sha512_core();
                dut.state_init, dut.state_update);
       $display("first_block     = 0x%01x, ready_flag    = 0x%01x, w_init    = 0x%01x",
                dut.first_block, dut.ready_flag, dut.w_init);
-      $display("round_ctr_inc       = 0x%01x, round_ctr_rst     = 0x%01x, round_ctr_reg = 0x%02x",
+      $display("round_ctr_inc   = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
                dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);
       $display("");
 
@@ -194,7 +194,7 @@ module tb_sha512_core();
 
       $display("State update values:");
       $display("w  = 0x%08x, k  = 0x%08x", dut.w_data, dut.k_data);
-      $display("t1 = 0x%08x, t2 = 0x%08x", dut.t1, dut.t2);
+      $display("t1 = 0x%08x, t2 = 0x%08x", dut.t1_new, dut.t2_new);
       $display("");
     end
   endtask // dump_dut_state
@@ -260,7 +260,7 @@ module tb_sha512_core();
       tb_next = 0;
       tb_next = 2'b00;
       tb_mode = 2'b00;
-      tb_block = {32{32'h00000000}};
+      tb_block = {1024'h0};
     end
   endtask // init_dut