[Cryptech-Commits] [core/hash/sha512] branch clock_speed updated: Connected all dangling dut ports in the core testbench. Fixed RTL code that caused event loop in Icarus. Does not change functionality.

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joachim at secworks.se pushed a commit to branch clock_speed
in repository core/hash/sha512.

The following commit(s) were added to refs/heads/clock_speed by this push:
     new 41286ea  Connected all dangling dut ports in the core testbench. Fixed RTL code that caused event loop in Icarus. Does not change functionality.
41286ea is described below

commit 41286ea5bde7d73154f98ddd4e06d5c6a8115129
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Tue Apr 3 12:59:12 2018 +0200

    Connected all dangling dut ports in the core testbench. Fixed RTL code that caused event loop in Icarus. Does not change functionality.
---
 src/rtl/sha512_core.v   | 14 +++++++-------
 src/tb/tb_sha512_core.v | 21 +++++++++++++++++++++
 2 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index 01f124d..e7ce7d9 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -536,18 +536,18 @@ module sha512_core(
   //----------------------------------------------------------------
   always @*
     begin : work_factor_ctr
-      work_factor_ctr_new  = 32'h00000000;
+      work_factor_ctr_new  = 32'h0;
       work_factor_ctr_we   = 0;
-      work_factor_ctr_done = 0;
+      work_factor_ctr_done = 1;
 
-      if (work_factor_ctr_reg == work_factor_num)
-        begin
-          work_factor_ctr_done = 1;
-        end
+      if (work_factor_ctr_reg < work_factor_num)
+        work_factor_ctr_done = 0;
+      else
+        work_factor_ctr_done = 1;
 
       if (work_factor_ctr_rst)
         begin
-          work_factor_ctr_new  = 32'h00000000;
+          work_factor_ctr_new  = 32'h0;
           work_factor_ctr_we   = 1;
         end
 
diff --git a/src/tb/tb_sha512_core.v b/src/tb/tb_sha512_core.v
index 8aeaa33..0a56b6f 100644
--- a/src/tb/tb_sha512_core.v
+++ b/src/tb/tb_sha512_core.v
@@ -86,10 +86,31 @@ module tb_sha512_core();
                    .next(tb_next),
                    .mode(tb_mode),
 
+                   .work_factor(1'b0),
+                   .work_factor_num(32'h0),
+
                    .block(tb_block),
 
                    .ready(tb_ready),
 
+                   .state_wr_data(32'h0),
+                   .state00_we(1'b0),
+                   .state01_we(1'b0),
+                   .state02_we(1'b0),
+                   .state03_we(1'b0),
+                   .state04_we(1'b0),
+                   .state05_we(1'b0),
+                   .state06_we(1'b0),
+                   .state07_we(1'b0),
+                   .state08_we(1'b0),
+                   .state09_we(1'b0),
+                   .state10_we(1'b0),
+                   .state11_we(1'b0),
+                   .state12_we(1'b0),
+                   .state13_we(1'b0),
+                   .state14_we(1'b0),
+                   .state15_we(1'b0),
+
                    .digest(tb_digest),
                    .digest_valid(tb_digest_valid)
                  );

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