[Cryptech-Commits] [user/shatov/ecdh_fpga_model] branch master updated: No line continuation needed in Verilog.

git at cryptech.is git at cryptech.is
Mon Apr 2 23:24:35 UTC 2018


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meisterpaul1 at yandex.ru pushed a commit to branch master
in repository user/shatov/ecdh_fpga_model.

The following commit(s) were added to refs/heads/master by this push:
     new ddf42e1  No line continuation needed in Verilog.
ddf42e1 is described below

commit ddf42e1abc77ae11757f69d8489f0ce9d6a9c0d0
Author: Pavel V. Shatov (Meister) <meisterpaul1 at yandex.ru>
AuthorDate: Tue Apr 3 02:23:19 2018 +0300

    No line continuation needed in Verilog.
---
 test_vectors/ecdh_test_vectors.v    | 32 ++++++++++++++++----------------
 test_vectors/format_test_vectors.py | 16 ++++++++--------
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/test_vectors/ecdh_test_vectors.v b/test_vectors/ecdh_test_vectors.v
index a1bc092..83ea5a2 100644
--- a/test_vectors/ecdh_test_vectors.v
+++ b/test_vectors/ecdh_test_vectors.v
@@ -1,73 +1,73 @@
 /* Generated automatically, do not edit. */
 
-localparam [255:0] P_256_DA \
+localparam [255:0] P_256_DA 
 	{32'h404d4afa, 32'h3865a3d6, 32'hf921ccb4, 32'h7cdea4e9, 
 	 32'h276c3d45, 32'h6e84d196, 32'h63324daf, 32'h8c5e2f44};
 
-localparam [255:0] P_256_QA_X \
+localparam [255:0] P_256_QA_X 
 	{32'h6f3b61af, 32'h3d79d1b6, 32'h7c128369, 32'h1fe8e872, 
 	 32'hde81e17a, 32'h06b5d4e1, 32'haeedcd57, 32'h09bf1d1b};
 
-localparam [255:0] P_256_QA_Y \
+localparam [255:0] P_256_QA_Y 
 	{32'hd1345bcc, 32'ha022ea89, 32'h53b04c2d, 32'h11fc24f8, 
 	 32'h0b3b7f84, 32'h7b79deee, 32'hd92ec430, 32'hd8ec3c98};
 
-localparam [255:0] P_256_DB \
+localparam [255:0] P_256_DB 
 	{32'h7159a43b, 32'he8322471, 32'h19feaeb2, 32'h7a92466e, 
 	 32'h2b07c8df, 32'h29bbd7ea, 32'hd3232af8, 32'h44995a95};
 
-localparam [255:0] P_256_QB_X \
+localparam [255:0] P_256_QB_X 
 	{32'h0514608d, 32'hc2dc6a21, 32'h74b084d6, 32'h168aad13, 
 	 32'h4acd3f52, 32'h6e49dc32, 32'hbf9872aa, 32'ha4be99d9};
 
-localparam [255:0] P_256_QB_Y \
+localparam [255:0] P_256_QB_Y 
 	{32'h724afa75, 32'h4c672b71, 32'he87c9bda, 32'he1e2b15f, 
 	 32'h784f480f, 32'heb62040e, 32'h281953bd, 32'hea382946};
 
-localparam [255:0] P_256_S_X \
+localparam [255:0] P_256_S_X 
 	{32'ha001c11b, 32'h0d04b6c3, 32'hbe99551e, 32'h9115b811, 
 	 32'h0a41a0b7, 32'h59c3e3f2, 32'hfb636df1, 32'heb0e9a42};
 
-localparam [255:0] P_256_S_Y \
+localparam [255:0] P_256_S_Y 
 	{32'h14ed5674, 32'h62b6ba27, 32'h2ba0e01b, 32'h2647d725, 
 	 32'h5919bf5e, 32'hcbb542f7, 32'h659d40de, 32'h324524ac};
 
-localparam [383:0] P_384_DA \
+localparam [383:0] P_384_DA 
 	{32'he733d9db, 32'hb8867b57, 32'h3cbbc0bd, 32'h899c88db, 
 	 32'h669322e8, 32'h0435c1a4, 32'he2b0ddb1, 32'h5e757371, 
 	 32'hf684a595, 32'h05d923c8, 32'hbf96dc11, 32'hc3ae505a};
 
-localparam [383:0] P_384_QA_X \
+localparam [383:0] P_384_QA_X 
 	{32'h8b852708, 32'h18311f7f, 32'h1ef2f04d, 32'hb38e68b2, 
 	 32'h3c008bfb, 32'h14e20cb0, 32'h37efa421, 32'hc3c3df6d, 
 	 32'ha37c484e, 32'h855da981, 32'hda866580, 32'h7203ff36};
 
-localparam [383:0] P_384_QA_Y \
+localparam [383:0] P_384_QA_Y 
 	{32'hd748f515, 32'hef7f2672, 32'h0ce8a70e, 32'h20827296, 
 	 32'h8ee6a89a, 32'haeccd8fb, 32'h61b35364, 32'hc70dfb48, 
 	 32'heb5c685c, 32'h810bd9cb, 32'h2d184fb1, 32'h096ab30f};
 
-localparam [383:0] P_384_DB \
+localparam [383:0] P_384_DB 
 	{32'h5601820d, 32'h705224a5, 32'hdd6ddb13, 32'he0a15e76, 
 	 32'h869e6abe, 32'h37ba2235, 32'h792af9f6, 32'ha9bf114a, 
 	 32'hd1fd319d, 32'hd8181e06, 32'h44f15448, 32'h4e73a75a};
 
-localparam [383:0] P_384_QB_X \
+localparam [383:0] P_384_QB_X 
 	{32'h37ab556d, 32'h0652c6b9, 32'he352c643, 32'h4502be19, 
 	 32'h9fb9c50f, 32'h2ade049b, 32'h06e50c30, 32'hcdab0673, 
 	 32'h69efe0c0, 32'h6e114a76, 32'hf1338175, 32'hdb4f4982};
 
-localparam [383:0] P_384_QB_Y \
+localparam [383:0] P_384_QB_Y 
 	{32'h21cddae0, 32'hf117b656, 32'h7c9d477b, 32'hc1fc5d24, 
 	 32'h3b26651e, 32'h1406f1ee, 32'hb3418552, 32'h739c9395, 
 	 32'h6774c84d, 32'h20cedc15, 32'h92fd5de0, 32'h4bbf98ad};
 
-localparam [383:0] P_384_S_X \
+localparam [383:0] P_384_S_X 
 	{32'h15ac62cb, 32'hbb51e1ed, 32'hd41d489f, 32'hdfa05d45, 
 	 32'h115f4ef2, 32'h269fbd26, 32'h3f6c7364, 32'h673f0b19, 
 	 32'h489e8a7b, 32'hdfad6d40, 32'h277edf9f, 32'h62220c51};
 
-localparam [383:0] P_384_S_Y \
+localparam [383:0] P_384_S_Y 
 	{32'ha0b846fe, 32'ha76973b4, 32'h12dfae76, 32'h2b3b6587, 
 	 32'hf62be0a3, 32'h73da36ef, 32'h8992e7c9, 32'h6cf7619d, 
 	 32'ha2d6c0a2, 32'hd31ad05d, 32'hb3a16a95, 32'h0cb7055f};
diff --git a/test_vectors/format_test_vectors.py b/test_vectors/format_test_vectors.py
index 1389711..66f93f8 100644
--- a/test_vectors/format_test_vectors.py
+++ b/test_vectors/format_test_vectors.py
@@ -94,16 +94,16 @@ def format_verilog_include(f, curve, da, qax, qay, db, qbx, qby, sx, sy):
 		msb_index = "383"
 	
 		# write all numbers in vector
-	format_verilog_concatenation(f, da,  "localparam [" + msb_index + ":0] " + curve_str + "_DA"   + " \\\n")
-	format_verilog_concatenation(f, qax, "localparam [" + msb_index + ":0] " + curve_str + "_QA_X" + " \\\n")
-	format_verilog_concatenation(f, qay, "localparam [" + msb_index + ":0] " + curve_str + "_QA_Y" + " \\\n")
+	format_verilog_concatenation(f, da,  "localparam [" + msb_index + ":0] " + curve_str + "_DA"   + " \n")
+	format_verilog_concatenation(f, qax, "localparam [" + msb_index + ":0] " + curve_str + "_QA_X" + " \n")
+	format_verilog_concatenation(f, qay, "localparam [" + msb_index + ":0] " + curve_str + "_QA_Y" + " \n")
 	
-	format_verilog_concatenation(f, db,  "localparam [" + msb_index + ":0] " + curve_str + "_DB"   + " \\\n")
-	format_verilog_concatenation(f, qbx, "localparam [" + msb_index + ":0] " + curve_str + "_QB_X" + " \\\n")
-	format_verilog_concatenation(f, qby, "localparam [" + msb_index + ":0] " + curve_str + "_QB_Y" + " \\\n")
+	format_verilog_concatenation(f, db,  "localparam [" + msb_index + ":0] " + curve_str + "_DB"   + " \n")
+	format_verilog_concatenation(f, qbx, "localparam [" + msb_index + ":0] " + curve_str + "_QB_X" + " \n")
+	format_verilog_concatenation(f, qby, "localparam [" + msb_index + ":0] " + curve_str + "_QB_Y" + " \n")
 
-	format_verilog_concatenation(f, sx,  "localparam [" + msb_index + ":0] " + curve_str + "_S_X"  + " \\\n")
-	format_verilog_concatenation(f, sy,  "localparam [" + msb_index + ":0] " + curve_str + "_S_Y"  + " \\\n")
+	format_verilog_concatenation(f, sx,  "localparam [" + msb_index + ":0] " + curve_str + "_S_X"  + " \n")
+	format_verilog_concatenation(f, sy,  "localparam [" + msb_index + ":0] " + curve_str + "_S_Y"  + " \n")
 
 #
 # nicely format multi-word integer into C array initializer

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