[Cryptech-Commits] [core/platform/alpha] branch master updated: Separate FMC test from mainline top-level module.
git at cryptech.is
git at cryptech.is
Thu Sep 21 21:07:23 UTC 2017
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paul at psgd.org pushed a commit to branch master
in repository core/platform/alpha.
The following commit(s) were added to refs/heads/master by this push:
new a4e91b6 Separate FMC test from mainline top-level module.
a4e91b6 is described below
commit a4e91b6221f75045dd1d97362e9d12c590ebc15a
Author: Paul Selkirk <paul at psgd.org>
AuthorDate: Thu Sep 21 09:20:21 2017 -0400
Separate FMC test from mainline top-level module.
---
build/Makefile | 8 +-
build/{Makefile => Makefile.test} | 53 +-------
rtl/{alpha_fmc_top.v => alpha_fmc_test.v} | 38 +-----
rtl/alpha_fmc_top.v | 69 -----------
ucf/alpha_fmc_test.ucf | 199 ++++++++++++++++++++++++++++++
5 files changed, 209 insertions(+), 158 deletions(-)
diff --git a/build/Makefile b/build/Makefile
index 763ad5e..4e3a9bb 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -25,10 +25,10 @@ all: $(project).bit
CONFIG = $(CORE_TREE)/platform/common/config
CONFIG_BOARD = alpha
CONFIG_PROJECT = hsm
-CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD) -p $(CONFIG_PROJECT)
+CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD)
core_selector.v core_vfiles.mk:
- $(CONFIG_GEN)
+ $(CONFIG_GEN) -p $(CONFIG_PROJECT)
# Build some different configurations
@@ -56,6 +56,10 @@ hsm:
$(CONFIG_GEN) -p hsm
$(MAKE) project=$(project)_hsm ucf=$(ucf)
+hsm-super:
+ $(CONFIG_GEN) -p hsm-super
+ $(MAKE) project=$(project)_hsm-super ucf=$(ucf)
+
# Verilog files that always go with builds on this platform.
vfiles = \
diff --git a/build/Makefile b/build/Makefile.test
similarity index 55%
copy from build/Makefile
copy to build/Makefile.test
index 763ad5e..7243bd5 100644
--- a/build/Makefile
+++ b/build/Makefile.test
@@ -9,7 +9,7 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0))
# Parameters to xilinx.mk.
-project ?= alpha_fmc
+project ?= alpha_fmc_test
vendor = xilinx
family = artix7
part = xc7a200tfbg484-3
@@ -20,50 +20,13 @@ ucf ?= ../ucf/$(project).ucf
all: $(project).bit
-# Build the default core_selector if it doesn't already exist.
-
-CONFIG = $(CORE_TREE)/platform/common/config
-CONFIG_BOARD = alpha
-CONFIG_PROJECT = hsm
-CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD) -p $(CONFIG_PROJECT)
-
-core_selector.v core_vfiles.mk:
- $(CONFIG_GEN)
-
-# Build some different configurations
-
-bare:
- $(CONFIG_GEN) -p bare
- $(MAKE) project=$(project)_bare ucf=$(ucf)
-
-trng:
- $(CONFIG_GEN) -p trng
- $(MAKE) project=$(project)_trng ucf=$(ucf)
-
-hash:
- $(CONFIG_GEN) -p hash
- $(MAKE) project=$(project)_hash ucf=$(ucf)
-
-rsa:
- $(CONFIG_GEN) -p rsa
- $(MAKE) project=$(project)_rsa ucf=$(ucf)
-
-mkmif:
- $(CONFIG_GEN) -p mkmif
- $(MAKE) project=$(project)_mkmif ucf=$(ucf)
-
-hsm:
- $(CONFIG_GEN) -p hsm
- $(MAKE) project=$(project)_hsm ucf=$(ucf)
-
# Verilog files that always go with builds on this platform.
vfiles = \
- $(CORE_TREE)/platform/alpha/rtl/alpha_fmc_top.v \
+ $(CORE_TREE)/platform/alpha/rtl/alpha_fmc_test.v \
$(CORE_TREE)/platform/alpha/rtl/alpha_regs.v \
$(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
- ./core_selector.v \
$(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
@@ -71,10 +34,6 @@ vfiles = \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_regs.v
-# Verilog files selected by the core configuration script.
-
--include ./core_vfiles.mk
-
include xilinx.mk
# 'clean' target collects files by project name, and we just broke that
@@ -88,11 +47,3 @@ junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \
*_summary.xml *_usage.xml
distclean: clean
- rm core_selector.v core_vfiles.mk
-
-# Fun extras for running verilator as a linter.
-
-VERILATOR_FLAGS = --lint-only --top-module $(top_module) -Wall -Wno-fatal -Wno-DECLFILENAME
-
-lint:
- verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/alpha/rtl/lint-dummy.v
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_test.v
similarity index 88%
copy from rtl/alpha_fmc_top.v
copy to rtl/alpha_fmc_test.v
index 79bfba8..182911e 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_test.v
@@ -1,6 +1,6 @@
//======================================================================
//
-// alpha_top.v
+// alpha_test.v
// ------------
// Top module for the Cryptech Alpha FPGA framework. This design
// allow us to run the FMC interface at one clock and cores including
@@ -108,17 +108,12 @@ module alpha_fmc_top
// FMC arbiter handles FMC access and transfers it into
// `sys_clk' clock domain.
//----------------------------------------------------------------
- //`define test
wire [23: 0] sys_fmc_addr; // address
wire sys_fmc_wren; // write enable
wire sys_fmc_rden; // read enable
wire [31: 0] sys_fmc_dout; // data output (from STM32 to FPGA)
-`ifdef test
reg [31: 0] sys_fmc_din; // data input (from FPGA to STM32)
-`else
- wire [31: 0] sys_fmc_din; // data input (from FPGA to STM32)
-`endif
fmc_arbiter #
(
@@ -160,7 +155,6 @@ module alpha_fmc_top
);
-`ifdef test
//----------------------------------------------------------------
// Dummy Register
//
@@ -222,37 +216,9 @@ module alpha_fmc_top
//
end
-`else // !`ifdef test
- //----------------------------------------------------------------
- // Core Selector
- //
- // This multiplexer is used to map different types of cores, such as
- // hashes, RNGs and ciphers to different regions (segments) of memory.
- //----------------------------------------------------------------
-
- core_selector cores
- (
- .sys_clk(sys_clk),
- .sys_rst_n(sys_rst_n),
-
- .sys_fmc_addr(sys_fmc_addr),
- .sys_fmc_wr(sys_fmc_wren),
- .sys_fmc_rd(sys_fmc_rden),
- .sys_write_data(sys_fmc_dout),
- .sys_read_data(sys_fmc_din),
-
- .noise(ct_noise),
-
- .mkm_sclk(mkm_sclk),
- .mkm_cs_n(mkm_cs_n),
- .mkm_do(mkm_do),
- .mkm_di(mkm_di)
- );
-`endif
-
//
- // Dummy assignment to bypass unconnected outpins pins check in BitGen
+ // Dummy assignments to bypass unconnected outpins pins check in BitGen
//
assign led_pins[3:1] = 3'b000;
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 79bfba8..03c2802 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -108,17 +108,12 @@ module alpha_fmc_top
// FMC arbiter handles FMC access and transfers it into
// `sys_clk' clock domain.
//----------------------------------------------------------------
- //`define test
wire [23: 0] sys_fmc_addr; // address
wire sys_fmc_wren; // write enable
wire sys_fmc_rden; // read enable
wire [31: 0] sys_fmc_dout; // data output (from STM32 to FPGA)
-`ifdef test
- reg [31: 0] sys_fmc_din; // data input (from FPGA to STM32)
-`else
wire [31: 0] sys_fmc_din; // data input (from FPGA to STM32)
-`endif
fmc_arbiter #
(
@@ -160,69 +155,6 @@ module alpha_fmc_top
);
-`ifdef test
- //----------------------------------------------------------------
- // Dummy Register
- //
- // General-purpose register to test FMC interface using STM32
- // demo program instead of core selector logic.
- //
- // This register is a bit tricky, but it allows testing of both
- // data and address buses. Reading from FPGA will always return
- // value, which is currently stored in the test register,
- // regardless of read transaction address. Writing to FPGA has
- // two variants: a) writing to address 0 will store output data
- // data value in the test register, b) writing to any non-zero
- // address will store _address_ of write transaction in the test
- // register.
- //
- // To test data bus, write some different patterns to address 0,
- // then readback from any address and compare.
- //
- // To test address bus, write anything to some different non-zero
- // addresses, then readback from any address and compare returned
- // value with previously written address.
- //
- //----------------------------------------------------------------
- reg [31: 0] test_reg;
-
-
-
- //
- // Noise Capture Register
- //
- reg [31: 0] noise_reg;
-
- always @(posedge sys_clk)
- //
- noise_reg <= {noise_reg[30:0], ct_noise};
-
-
-
- always @(posedge sys_clk)
- //
- if (sys_fmc_wren) begin
- //
- // when writing to address 0, store input data value
- //
- // when writing to non-zero address, store _address_
- // (padded with zeroes) instead of data
- //
- test_reg <= (sys_fmc_addr == {24{1'b0}}) ? sys_fmc_dout : {{8{1'b0}}, sys_fmc_addr};
- //
- end else if (sys_fmc_rden) begin
- //
- // always return current value, ignore address
- //
- sys_fmc_din <= (sys_fmc_addr == {24{1'b1}}) ? noise_reg : test_reg;
-
- // when reading from address 0, return the current value
- // when reading from other addresses, return the address
- //sys_fmc_din <= (sys_fmc_addr == {22{1'b0}}) ? test_reg : {{10{1'b0}}, sys_fmc_addr};
- //
- end
-
-`else // !`ifdef test
//----------------------------------------------------------------
// Core Selector
//
@@ -248,7 +180,6 @@ module alpha_fmc_top
.mkm_do(mkm_do),
.mkm_di(mkm_di)
);
-`endif
//
diff --git a/ucf/alpha_fmc_test.ucf b/ucf/alpha_fmc_test.ucf
new file mode 100644
index 0000000..34b2072
--- /dev/null
+++ b/ucf/alpha_fmc_test.ucf
@@ -0,0 +1,199 @@
+#======================================================================
+#
+# alpha_fmc.ucf
+# -------------------
+# Constraint file for implementing the Cryptech Alpha base
+# for the Xilinx Artix-7 200T on the Alpha.
+#
+#
+# Author: Pavel Shatov
+# Copyright (c) 2016, NORDUnet A/S All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# - Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# - Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# - Neither the name of the NORDUnet nor the names of its contributors may
+# be used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#======================================================================
+
+
+#--------------------------------------------------------------------------------
+# GCLK Timing (fixed at 50 MHz)
+#--------------------------------------------------------------------------------
+NET "gclk_pin" TNM_NET = TNM_gclk;
+TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
+
+
+#-------------------------------------------------------------------------------
+# FMC_CLK Timing (can be up to 90 MHz)
+#-------------------------------------------------------------------------------
+NET "fmc_clk" TNM_NET = TNM_fmc_clk;
+TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
+
+
+#-------------------------------------------------------------------------------
+# FPGA Pinout
+#-------------------------------------------------------------------------------
+#
+NET "led_pins<0>" LOC = "U3";
+NET "led_pins<1>" LOC = "T1";
+NET "led_pins<2>" LOC = "W22";
+NET "led_pins<3>" LOC = "AA20";
+#
+NET "led_pins<*>" IOSTANDARD = "LVCMOS33";
+NET "led_pins<*>" SLEW = SLOW;
+NET "led_pins<*>" DRIVE = 8;
+#
+NET "gclk_pin" LOC = "D17" | IOSTANDARD = "LVCMOS33" ;
+#
+NET "fmc_clk" LOC = "W11" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_ne1" LOC = "V5" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_noe" LOC = "W16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_nwe" LOC = "AA6" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_nl" LOC = "W17" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_nwait" LOC = "Y6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+#
+NET "fmc_a<0>" LOC = "Y17" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<1>" LOC = "AB16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<2>" LOC = "AA16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<3>" LOC = "Y16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<4>" LOC = "AB17" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<5>" LOC = "AA13" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<6>" LOC = "AB13" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<7>" LOC = "AA15" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<8>" LOC = "AB15" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<9>" LOC = "Y13" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<10>" LOC = "AA14" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<11>" LOC = "Y14" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<12>" LOC = "AB10" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<13>" LOC = "V2" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<14>" LOC = "AB12" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<15>" LOC = "AB8" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<16>" LOC = "AA9" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<17>" LOC = "AA8" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<18>" LOC = "Y7" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<19>" LOC = "AB21" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<20>" LOC = "AB22" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<21>" LOC = "AB20" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<22>" LOC = "Y21" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<23>" LOC = "Y22" | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<24>" LOC = "AB18" | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<25>" LOC = "AA19" | IOSTANDARD = "LVCMOS33" ;
+#
+NET "fmc_d<0>" LOC = "AB7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<1>" LOC = "AB6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<2>" LOC = "U1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<3>" LOC = "U2" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<4>" LOC = "AB11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<5>" LOC = "AA11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<6>" LOC = "Y11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<7>" LOC = "Y12" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<8>" LOC = "Y18" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<9>" LOC = "AA21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<10>" LOC = "W20" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<11>" LOC = "N15" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<12>" LOC = "U20" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<13>" LOC = "AA1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<14>" LOC = "AB1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<15>" LOC = "AB2" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<16>" LOC = "AB3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<17>" LOC = "Y3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<18>" LOC = "AA3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<19>" LOC = "AA5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<20>" LOC = "AB5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<21>" LOC = "Y4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<22>" LOC = "AA4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<23>" LOC = "V4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<24>" LOC = "W10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<25>" LOC = "R4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<26>" LOC = "W12" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<27>" LOC = "W14" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<28>" LOC = "V20" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<29>" LOC = "V18" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<30>" LOC = "R21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<31>" LOC = "P21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+
+NET "ct_noise" LOC = "W19" | IOSTANDARD = "LVCMOS33" ;
+
+#-------------------------------------------------------------------------------
+# FMC Input Timing
+#-------------------------------------------------------------------------------
+#
+# The following timing values were derived from pages 173-175 of the STM32F429
+# datasheet. Control signals NE1, NL and NWE all have different timing values.
+# Instead of writing individual constraints for every control signal, the most
+# strict constraint is applied to all control signals. This should not cause
+# any P&R issues, since Spartan-6 (and Artix-7) can handle 90 MHz easily.
+#
+# NOE signal is not constrained, since it drives "T" input of IOBUF primitive.
+#
+# Data and Address buses also have different timings, with Data bus timing being
+# more strict. The same approach is used here, i.e. timing for Data bus is
+# applied to Address bus too.
+#
+# Oh, and stupid datasheet doesn't explicitly specify hold time for the data bus!
+#
+
+NET "fmc_d<*>" TNM = "TNM_FMC_IN_DATA" ;
+NET "fmc_a<*>" TNM = "TNM_FMC_IN_ADDR" ;
+
+NET "fmc_ne1" TNM = "TNM_FMC_IN_CONTROL" ;
+NET "fmc_nl" TNM = "TNM_FMC_IN_CONTROL" ;
+NET "fmc_nwe" TNM = "TNM_FMC_IN_CONTROL" ;
+
+TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 3.0 ns VALID 6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 3.0 ns VALID 6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP "TNM_FMC_IN_CONTROL" OFFSET = IN 5.0 ns VALID 10.0 ns BEFORE "fmc_clk" RISING ;
+
+#-------------------------------------------------------------------------------
+# FMC Output Timing
+#-------------------------------------------------------------------------------
+#
+# NWAIT signal is not constrained, since it is polled by STM32.
+#
+
+NET "fmc_d<*>" TNM = "TNM_FMC_OUT_DATA" ;
+
+TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 16.7 ns AFTER "fmc_clk" FALLING;
+
+
+#-------------------------------------------------------------------------------
+# CDC Paths
+#-------------------------------------------------------------------------------
+INST "fmc/fmc_cdc/cdc_fmc_sys/src_ff" TNM = "TNM_from_fmc_clk";
+INST "fmc/fmc_cdc/cdc_fmc_sys/src_latch*" TNM = "TNM_from_fmc_clk";
+INST "fmc/fmc_cdc/cdc_fmc_sys/ff_sync*" TNM = "TNM_to_sys_clk";
+INST "fmc/fmc_cdc/cdc_fmc_sys/dst_latch*" TNM = "TNM_to_sys_clk";
+
+INST "fmc/fmc_cdc/cdc_sys_fmc/src_ff" TNM = "TNM_from_sys_clk";
+INST "fmc/fmc_cdc/cdc_sys_fmc/src_latch*" TNM = "TNM_from_sys_clk";
+INST "fmc/fmc_cdc/cdc_sys_fmc/ff_sync*" TNM = "TNM_to_fmc_clk";
+INST "fmc/fmc_cdc/cdc_sys_fmc/dst_latch*" TNM = "TNM_to_fmc_clk";
+
+TIMESPEC "TS_fmc_clk_2_sys_clk" = FROM "TNM_from_fmc_clk" TO "TNM_to_sys_clk" TIG;
+TIMESPEC "TS_sys_clk_2_fmc_clk" = FROM "TNM_from_sys_clk" TO "TNM_to_fmc_clk" TIG;
+
+#======================================================================
+# EOF alpha_fmc.ucf
+#======================================================================
--
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