[Cryptech-Commits] [core/cipher/aes] branch master updated: Adding the error port that went missing. Sloppy.

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joachim at secworks.se pushed a commit to branch master
in repository core/cipher/aes.

The following commit(s) were added to refs/heads/master by this push:
     new 2caa4d5  Adding the error port that went missing. Sloppy.
2caa4d5 is described below

commit 2caa4d54188338226494daa53d024a52572bd3a4
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Fri Dec 15 08:29:00 2017 +0100

    Adding the error port that went missing. Sloppy.
---
 src/rtl/aes.v   | 6 +++++-
 src/tb/tb_aes.v | 4 +++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index c2b333a..0d719d2 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -49,7 +49,8 @@ module aes(
            // Data ports.
            input wire  [7 : 0]  address,
            input wire  [31 : 0] write_data,
-           output wire [31 : 0] read_data
+           output wire [31 : 0] read_data,
+           output wire          error
           );
 
   //----------------------------------------------------------------
@@ -115,6 +116,7 @@ module aes(
   // Wires.
   //----------------------------------------------------------------
   reg [31 : 0]   tmp_read_data;
+  reg            tmp_error;
 
   wire           core_encdec;
   wire           core_init;
@@ -131,6 +133,7 @@ module aes(
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
   assign read_data = tmp_read_data;
+  assign error     = tmp_error;
 
   assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
                      key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
@@ -227,6 +230,7 @@ module aes(
       key_we        = 1'b0;
       block_we      = 1'b0;
       tmp_read_data = 32'h0;
+      tmp_error     = 1'b0;
 
       if (cs)
         begin
diff --git a/src/tb/tb_aes.v b/src/tb/tb_aes.v
index ae25130..188a21a 100644
--- a/src/tb/tb_aes.v
+++ b/src/tb/tb_aes.v
@@ -110,6 +110,7 @@ module tb_aes();
   reg [7  : 0]  tb_address;
   reg [31 : 0]  tb_write_data;
   wire [31 : 0] tb_read_data;
+  wire          tb_error;
 
 
   //----------------------------------------------------------------
@@ -122,7 +123,8 @@ module tb_aes();
            .we(tb_we),
            .address(tb_address),
            .write_data(tb_write_data),
-           .read_data(tb_read_data)
+           .read_data(tb_read_data),
+           .error(tb_error)
           );
 
 

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