[Cryptech-Commits] [core/cipher/aes] branch master updated: Adding support for linting the AES core.
git at cryptech.is
git at cryptech.is
Thu Dec 14 15:14:15 UTC 2017
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joachim at secworks.se pushed a commit to branch master
in repository core/cipher/aes.
The following commit(s) were added to refs/heads/master by this push:
new 67cd02c Adding support for linting the AES core.
67cd02c is described below
commit 67cd02c98626fc526c9e5e1790e049177190eab8
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Thu Dec 14 16:14:03 2017 +0100
Adding support for linting the AES core.
---
toolruns/Makefile | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/toolruns/Makefile b/toolruns/Makefile
index 105524e..835a92f 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -52,6 +52,7 @@ TB_ENCIPHER_SRC =../src/tb/tb_aes_encipher_block.v
TB_DECIPHER_SRC =../src/tb/tb_aes_decipher_block.v
CC=iverilog
+LINT=verilator
all: top.sim core.sim keymem.sim encipher.sim decipher.sim
@@ -96,6 +97,10 @@ sim-top: top.sim
./top.sim
+lint:
+ verilator +1364-2001ext+ --lint-only -Wall $(TOP_SRC)
+
+
clean:
rm -f decipher.sim
rm -f encipher.sim
@@ -110,6 +115,7 @@ help:
@echo "Supported targets:"
@echo "------------------"
@echo "all: Build all simulation targets."
+ @echo "lint: Lint all rtl source files."
@echo "top.sim: Build top level simulation target."
@echo "core.sim: Build core level simulation target."
@echo "keymem.sim: Build key memory simulation target."
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