[Cryptech-Commits] [sw/stm32] branch master updated: add bit-for-bit testing of FMC address and data bus

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fredrik at thulin.net pushed a commit to branch master
in repository sw/stm32.

The following commit(s) were added to refs/heads/master by this push:
       new  8f746c1   add bit-for-bit testing of FMC address and data bus
8f746c1 is described below

commit 8f746c1bba69550b966e3a0edd6ccc9c9877db55
Author: Fredrik Thulin <fredrik at thulin.net>
AuthorDate: Mon Sep 5 09:45:13 2016 +0200

    add bit-for-bit testing of FMC address and data bus
---
 projects/cli-test/test-fmc.c | 100 +++++++++++++++++++++++++++----------------
 1 file changed, 64 insertions(+), 36 deletions(-)

diff --git a/projects/cli-test/test-fmc.c b/projects/cli-test/test-fmc.c
index ea9afef..b393dac 100644
--- a/projects/cli-test/test-fmc.c
+++ b/projects/cli-test/test-fmc.c
@@ -76,9 +76,27 @@ volatile uint32_t data_diff = 0;
 volatile uint32_t addr_diff = 0;
 
 
+static int _write_then_read(struct cli_def *cli, uint32_t addr, uint32_t *write_buf, uint32_t *read_buf)
+{
+    int ok;
+
+    ok = fmc_write_32(addr, write_buf);
+    if (ok != 0) {
+	cli_print(cli, "FMC write failed: 0x%x", ok);
+	return 0;
+    }
+    ok = fmc_read_32(0, read_buf);
+    if (ok != 0) {
+	cli_print(cli, "FMC read failed: 0x%x", ok);
+	return 0;
+    }
+
+    return 1;
+}
+
 int test_fpga_data_bus(struct cli_def *cli, uint32_t test_rounds)
 {
-    int c, ok;
+    int i, c;
     uint32_t rnd, buf;
     HAL_StatusTypeDef hal_result;
 
@@ -96,19 +114,8 @@ int test_fpga_data_bus(struct cli_def *cli, uint32_t test_rounds)
 	    break;
 	}
 
-	/* write value to fpga at address 0 */
-	ok = fmc_write_32(0, &rnd);
-	if (ok != 0) {
-	    cli_print(cli, "FMC write failed: 0x%x", ok);
-	    break;
-	}
-
-	/* read value from fpga */
-	ok = fmc_read_32(0, &buf);
-	if (ok != 0) {
-	    cli_print(cli, "FMC read failed: 0x%x", ok);
-	    break;
-	}
+	/* write value to fpga at address 0 and then read it back from the test register */
+	if (! _write_then_read(cli, 0, &rnd, &buf)) break;
 
 	/* compare (abort testing in case of error) */
 	data_diff = buf ^ rnd;
@@ -124,16 +131,31 @@ int test_fpga_data_bus(struct cli_def *cli, uint32_t test_rounds)
 
     if (! data_diff) {
 	cli_print(cli, "Sample of data bus test data: expected 0x%lx got 0x%lx", rnd, buf);
+    } else {
+	uint32_t data;
+        cli_print(cli, "\nFMC data bus per-bit analysis:");
+        for (i = 0; i < 31; i++) {
+            data = 1 << i;
+
+	    if (! _write_then_read(cli, 0, &data, &buf)) break;
+
+	    if (data == buf) {
+	        cli_print(cli, "Data 0x%08lx (FMC_D%02i) - OK", data, i + 1);
+	    } else {
+	        cli_print(cli, "Data 0x%08lx (FMC_D%02i) - FAIL (read 0x%08lx)", data, i + 1, buf);
+	    }
+        }
     }
 
+
     /* return number of successful tests */
     return c;
 }
 
 int test_fpga_address_bus(struct cli_def *cli, uint32_t test_rounds)
 {
-    int c, ok;
-    uint32_t rnd, buf;
+    int i, c;
+    uint32_t addr, buf, dummy = 1;
     HAL_StatusTypeDef hal_result;
 
     /* initialize stm32 rng */
@@ -144,31 +166,22 @@ int test_fpga_address_bus(struct cli_def *cli, uint32_t test_rounds)
     for (c = 0; c < test_rounds; c++) {
 	addr_diff = 0;
 	/* try to generate "random" number */
-	hal_result = HAL_RNG_GenerateRandomNumber(&rng_inst, &rnd);
+	hal_result = HAL_RNG_GenerateRandomNumber(&rng_inst, &addr);
 	if (hal_result != HAL_OK) break;
 
 	/* there are 26 physicaly connected address lines on the alpha,
 	   but "only" 24 usable for now (the top two ones are used by FMC
 	   to choose bank, and we only have one bank set up currently)
 	*/
-	rnd &= 0x3fffffc;
+	addr &= 0x3fffffc;
 
 	/* don't test zero addresses (fpga will store data, not address) */
-	if (rnd == 0) continue;
+	if (addr == 0) continue;
 
-	/* write dummy value to fpga at some non-zero address */
-	ok = fmc_write_32(rnd, &buf);
-	if (ok != 0) {
-	    cli_print(cli, "FMC write failed: 0x%x", ok);
-	    break;
-	}
-
-	/* read value from fpga */
-	ok = fmc_read_32(0, &buf);
-	if (ok != 0) {
-	    cli_print(cli, "FMC read failed: 0x%x", ok);
-	    break;
-	}
+	/* write dummy value to fpga at some non-zero address and then read from the
+	   test register to see what address the FPGA thought we wrote to
+	*/
+	if (! _write_then_read(cli, addr, &dummy, &buf)) break;
 
 	/* fpga receives address of 32-bit word, while we need
 	   byte address here to compare
@@ -176,9 +189,9 @@ int test_fpga_address_bus(struct cli_def *cli, uint32_t test_rounds)
 	buf <<= 2;
 
 	/* compare (abort testing in case of error) */
-	addr_diff = buf ^ rnd;
+	addr_diff = buf ^ addr;
 	if (addr_diff) {
-	    cli_print(cli, "Address bus FAIL: expected 0x%lx got 0x%lx", rnd, buf);
+	    cli_print(cli, "Address bus FAIL: expected 0x%lx got 0x%lx", addr, buf);
 	    uart_send_string2(STM_UART_MGMT, (char *) "Binary diff: ");
 	    uart_send_number2(STM_UART_MGMT, addr_diff, 32, 2);
 	    uart_send_string2(STM_UART_MGMT, "\r\n");
@@ -188,10 +201,25 @@ int test_fpga_address_bus(struct cli_def *cli, uint32_t test_rounds)
     }
 
     if (! addr_diff) {
-	cli_print(cli, "Sample of address bus test data: expected 0x%lx got 0x%lx", rnd, buf);
+	cli_print(cli, "Sample of address bus test data: expected 0x%lx got 0x%lx", addr, buf);
+    } else {
+        cli_print(cli, "\nFMC address bus per-bit analysis:");
+        for (i = 0; i < 23; i++) {
+	    uint32_t shifted_addr;
+            addr = 1 << i;
+
+	    shifted_addr = addr << 2;
+
+	    if (! _write_then_read(cli, shifted_addr, &dummy, &buf)) break;
+
+	    if (addr == buf) {
+	        cli_print(cli, "Address 0x%08lx (FMC_A%02i) - OK", addr, i + 1);
+	    } else {
+	        cli_print(cli, "Address 0x%08lx (FMC_A%02i) - FAIL (read 0x%08lx)", addr, i + 1, buf);
+	    }
+        }
     }
 
     /* return number of successful tests */
     return c;
 }
-

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