[Cryptech-Commits] [core/hash/sha256] branch master updated: Fixed long constants and instead rely on zero extend in Verilog.

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joachim at secworks.se pushed a commit to branch master
in repository core/hash/sha256.

The following commit(s) were added to refs/heads/master by this push:
       new  0e90cfa   Fixed long constants and instead rely on zero extend in Verilog.
0e90cfa is described below

commit 0e90cfa1f076b8660610dfd3930ef1b37a1fb41e
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Tue May 31 13:30:12 2016 +0200

    Fixed long constants and instead rely on zero extend in Verilog.
---
 src/rtl/sha256.v | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/rtl/sha256.v b/src/rtl/sha256.v
index 7e1035f..1f9e75e 100644
--- a/src/rtl/sha256.v
+++ b/src/rtl/sha256.v
@@ -236,24 +236,24 @@ module sha256(
           init_reg         <= 0;
           next_reg         <= 0;
           ready_reg        <= 0;
-          digest_reg       <= 256'h0000000000000000000000000000000000000000000000000000000000000000;
+          digest_reg       <= 256'h0;
           digest_valid_reg <= 0;
-          block0_reg       <= 32'h00000000;
-          block1_reg       <= 32'h00000000;
-          block2_reg       <= 32'h00000000;
-          block3_reg       <= 32'h00000000;
-          block4_reg       <= 32'h00000000;
-          block5_reg       <= 32'h00000000;
-          block6_reg       <= 32'h00000000;
-          block7_reg       <= 32'h00000000;
-          block8_reg       <= 32'h00000000;
-          block9_reg       <= 32'h00000000;
-          block10_reg      <= 32'h00000000;
-          block11_reg      <= 32'h00000000;
-          block12_reg      <= 32'h00000000;
-          block13_reg      <= 32'h00000000;
-          block14_reg      <= 32'h00000000;
-          block15_reg      <= 32'h00000000;
+          block0_reg       <= 32'h0;
+          block1_reg       <= 32'h0;
+          block2_reg       <= 32'h0;
+          block3_reg       <= 32'h0;
+          block4_reg       <= 32'h0;
+          block5_reg       <= 32'h0;
+          block6_reg       <= 32'h0;
+          block7_reg       <= 32'h0;
+          block8_reg       <= 32'h0;
+          block9_reg       <= 32'h0;
+          block10_reg      <= 32'h0;
+          block11_reg      <= 32'h0;
+          block12_reg      <= 32'h0;
+          block13_reg      <= 32'h0;
+          block14_reg      <= 32'h0;
+          block15_reg      <= 32'h0;
         end
       else
         begin

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