[Cryptech-Commits] [core/util/mkmif] 03/03: Move into the 'official' tree, fix typos, correct copyright dates.

git at cryptech.is git at cryptech.is
Tue May 17 13:08:56 UTC 2016


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paul at psgd.org pushed a commit to branch master
in repository core/util/mkmif.

commit fd1dd73410ba6ca3d082ff61e4b39d6e8c2de35e
Author: Paul Selkirk <paul at psgd.org>
AuthorDate: Tue May 17 15:05:24 2016 +0200

    Move into the 'official' tree, fix typos, correct copyright dates.
---
 LICENSE.txt            |  2 +-
 README.md              | 21 ++++++++++-----------
 src/rtl/mkmif.v        |  2 +-
 src/rtl/mkmif_core.v   |  2 +-
 src/rtl/mkmif_spi.v    |  2 +-
 src/tb/tb_mkmif.v      |  2 +-
 src/tb/tb_mkmif_core.v |  2 +-
 src/tb/tb_mkmif_spi.v  |  2 +-
 toolruns/Makefile      |  2 +-
 9 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/LICENSE.txt b/LICENSE.txt
index 50b916a..5c4080c 100644
--- a/LICENSE.txt
+++ b/LICENSE.txt
@@ -1,4 +1,4 @@
-Copyright (c) 2011, NORDUnet A/S All rights reserved.
+Copyright (c) 2016, NORDUnet A/S All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
 modification, are permitted provided that the following conditions are
diff --git a/README.md b/README.md
index 771cb6f..c5beab1 100644
--- a/README.md
+++ b/README.md
@@ -6,21 +6,21 @@ serial SRAM with a SPI interface.
 
 
 ## Purpose and Functionality ##
-The Master Key Memory is where a cryptographic master key is stored. the
+The Master Key Memory is where a cryptographic master key is stored. The
 key is used (for example) to cryptographically wrap other keys and
 secrets. By wiping the MKM and thus the master key, the wrapped secrets
 are protected against leakage to a local attacker that physically breaks
-an actuve tamper detect shield.
+an active tamper detect shield.
 
-The core will in future versions provide functionality to autonomosly
-protect against memory remanence effects by rotating bits in stored data
+The core will in future versions provide functionality to autonomously
+protect against memory remanence effects by rotating bits in stored data,
 and moving data to different addresses in the external memory. The core
-will also be able to automously zeroise the memory when given an alarm
+will also be able to autonomously zeroise the memory when given an alarm
 signal.
 
 The current version however simply provides an interface to the slower,
 serial memory including initializing the memory in the correct mode. The
-core supports three commands: read word, write word and initalize
+core supports three commands: read word, write word, and initialize
 memory.
 
 
@@ -29,7 +29,7 @@ The SPI clock is generated by the core clock (clk) divided by the
 SPI clock divisor * 2 (the divisor is the half period in cycles). The
 default divisor is set to generate an SPI clock of less than 1 MHz when
 the core clock is 50 MHz. For other speeds and other
-core frequencies the divisor will have to be adjusted.
+core frequencies, the divisor will have to be adjusted.
 
 The core will only read and write complete 32-bit words.
 
@@ -45,12 +45,11 @@ The implementation is divided into three parts:
   read data. The SPI interface also generates the SPI clock and chip
   enable.
 
-- A command handler core that tha read and write words as well as send
+- A Microchip-specific command handler that sends the read, write, and
   init commands to the memory using the SPI interface.
 
 - An API interface that provides the ability to configure the SPI clock
-  speed, setting the address to be read or written and data access.
-
+  speed, set the address to read or write, and data access.
 
 The current implementation will initiate the Microchip memory directly
 after reset and set the memory in sequential mode. This means that it
@@ -94,7 +93,7 @@ to remove the need to update the address between bytes.
 **(2016-05-10)**
 
 The core has now been verified in a Xilinx Spartan-6 FPGA and the target
-Microchip memory connected to the FPGA.memory. Read and write access has
+Microchip memory connected to the FPGA memory. Read and write access has
 successfully been performed with SPI clock speeds from 300 Hz to 10 MHz.
 
 
diff --git a/src/rtl/mkmif.v b/src/rtl/mkmif.v
index 4f44878..8e29f14 100644
--- a/src/rtl/mkmif.v
+++ b/src/rtl/mkmif.v
@@ -12,7 +12,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
diff --git a/src/rtl/mkmif_core.v b/src/rtl/mkmif_core.v
index 0f90bf0..6646aad 100644
--- a/src/rtl/mkmif_core.v
+++ b/src/rtl/mkmif_core.v
@@ -12,7 +12,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
diff --git a/src/rtl/mkmif_spi.v b/src/rtl/mkmif_spi.v
index fc80470..168a4e5 100644
--- a/src/rtl/mkmif_spi.v
+++ b/src/rtl/mkmif_spi.v
@@ -12,7 +12,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
diff --git a/src/tb/tb_mkmif.v b/src/tb/tb_mkmif.v
index 4142574..31b26c5 100644
--- a/src/tb/tb_mkmif.v
+++ b/src/tb/tb_mkmif.v
@@ -6,7 +6,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
diff --git a/src/tb/tb_mkmif_core.v b/src/tb/tb_mkmif_core.v
index 48042f4..6311515 100644
--- a/src/tb/tb_mkmif_core.v
+++ b/src/tb/tb_mkmif_core.v
@@ -6,7 +6,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
diff --git a/src/tb/tb_mkmif_spi.v b/src/tb/tb_mkmif_spi.v
index 763defe..a154e0a 100644
--- a/src/tb/tb_mkmif_spi.v
+++ b/src/tb/tb_mkmif_spi.v
@@ -6,7 +6,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2011, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
diff --git a/toolruns/Makefile b/toolruns/Makefile
index 4d36b5c..8c0e534 100644
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -5,7 +5,7 @@
 # Makefile for building the mkmif core.
 #
 #
-# Copyright (c) 2011, NORDUnet A/S All rights reserved.
+# Copyright (c) 2016, NORDUnet A/S All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are



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