[Cryptech-Commits] [core/platform/alpha] branch master updated: Move core config script here from core/platform/common, and adapt to the larger fmc address bus.
git at cryptech.is
git at cryptech.is
Tue Jun 14 20:44:02 UTC 2016
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paul at psgd.org pushed a commit to branch master
in repository core/platform/alpha.
The following commit(s) were added to refs/heads/master by this push:
new fc8be80 Move core config script here from core/platform/common, and adapt to the larger fmc address bus.
fc8be80 is described below
commit fc8be8024560bb77221758b0351c3de7b4ea6e93
Author: Paul Selkirk <paul at psgd.org>
AuthorDate: Tue Jun 14 16:43:22 2016 -0400
Move core config script here from core/platform/common, and adapt to the larger fmc address bus.
---
build/Makefile | 18 +-
build/config.cfg | 144 +++++++++++++
build/config.py | 573 ++++++++++++++++++++++++++++++++++++++++++++++++++++
rtl/alpha_fmc_top.v | 6 +-
4 files changed, 731 insertions(+), 10 deletions(-)
diff --git a/build/Makefile b/build/Makefile
index aed01df..d5d4871 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -22,32 +22,36 @@ all: $(project).bit
# Build the default core_selector if it doesn't already exist.
-CONFIG = $(CORE_TREE)/platform/common/config
+CONFIG = .
core_selector.v core_vfiles.mk:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg
+ $(CONFIG)/config.py
# Build some different configurations
bare:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+ $(CONFIG)/config.py -s bare
$(MAKE) project=$(project)_bare ucf=$(ucf)
trng:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+ $(CONFIG)/config.py -s trng
$(MAKE) project=$(project)_trng ucf=$(ucf)
hash:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+ $(CONFIG)/config.py -s hash
$(MAKE) project=$(project)_hash ucf=$(ucf)
rsa:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+ $(CONFIG)/config.py -s rsa
$(MAKE) project=$(project)_rsa ucf=$(ucf)
mkmif:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s mkmif
+ $(CONFIG)/config.py -s mkmif
$(MAKE) project=$(project)_mkmif ucf=$(ucf)
+hsm:
+ $(CONFIG)/config.py -s hsm
+ $(MAKE) project=$(project)_hsm ucf=$(ucf)
+
# Verilog files that always go with builds on this platform.
vfiles = \
diff --git a/build/config.cfg b/build/config.cfg
new file mode 100644
index 0000000..a7e3151
--- /dev/null
+++ b/build/config.cfg
@@ -0,0 +1,144 @@
+# Config file for the Cryptech Novena FPGA framework.
+#
+# Variables used in this file:
+#
+# default-section: Name of the configuration to build if the user
+# doesn't specify one. Only meaningful in the default section.
+#
+# cores: A list of cores to build. Use with the --section option.
+#
+# vfiles: A list of Verilog files to include in the vfiles list when
+# including a particular core. All (optional) cores must have a
+# vfiles option, so that the configuration program knows what to put
+# into core_vfiles.mk.
+#
+# requires: A list of other cores whose vfiles must be loaded to build
+# this core. This has no effect on the generated core_selector.v
+# file, and has no effect at all if an instance of a core named here
+# is already included in the build.
+#
+# error_wire: boolean indicating whether the core wants a error wire.
+#
+# block_memory: boolean indicating whether the core uses block memory.
+# Effect of this is a bit strange: setting it triggers generation of
+# a one-cycle timing delay for every core in this build that does
+# *not* use block memory. When no cores in the build use block
+# memory, the delay isn't necessary and is therefore omitted.
+
+[default]
+default-section = hsm
+
+# for quick builds to test the bus
+[bare]
+cores =
+
+[hash]
+cores = sha1 sha256 sha512
+
+[trng]
+cores = trng
+
+[modexp]
+cores = modexpa7
+
+[mkmif]
+cores = mkmif
+
+[rsa]
+cores = mkmif sha256 aes trng modexpa7
+
+# make me one with everything
+[hsm]
+cores = mkmif sha1 sha256 sha512 aes trng modexpa7
+
+# include multiple of the same core
+[multi-test]
+cores = sha256 aes aes chacha aes
+
+[sha1]
+vfiles =
+ hash/sha1/src/rtl/sha1.v
+ hash/sha1/src/rtl/sha1_core.v
+ hash/sha1/src/rtl/sha1_w_mem.v
+
+[sha256]
+vfiles =
+ hash/sha256/src/rtl/sha256.v
+ hash/sha256/src/rtl/sha256_core.v
+ hash/sha256/src/rtl/sha256_k_constants.v
+ hash/sha256/src/rtl/sha256_w_mem.v
+
+[sha512]
+vfiles =
+ hash/sha512/src/rtl/sha512.v
+ hash/sha512/src/rtl/sha512_core.v
+ hash/sha512/src/rtl/sha512_h_constants.v
+ hash/sha512/src/rtl/sha512_k_constants.v
+ hash/sha512/src/rtl/sha512_w_mem.v
+
+[trng]
+requires = chacha sha512
+vfiles =
+ rng/avalanche_entropy/src/rtl/avalanche_entropy.v
+ rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v
+ rng/rosc_entropy/src/rtl/rosc.v
+ rng/rosc_entropy/src/rtl/rosc_entropy.v
+ rng/rosc_entropy/src/rtl/rosc_entropy_core.v
+ rng/trng/src/rtl/trng.v
+ rng/trng/src/rtl/trng_csprng.v
+ rng/trng/src/rtl/trng_csprng_fifo.v
+ rng/trng/src/rtl/trng_mixer.v
+
+[aes]
+vfiles =
+ cipher/aes/src/rtl/aes.v
+ cipher/aes/src/rtl/aes_core.v
+ cipher/aes/src/rtl/aes_decipher_block.v
+ cipher/aes/src/rtl/aes_encipher_block.v
+ cipher/aes/src/rtl/aes_inv_sbox.v
+ cipher/aes/src/rtl/aes_key_mem.v
+ cipher/aes/src/rtl/aes_sbox.v
+
+[chacha]
+vfiles =
+ cipher/chacha/src/rtl/chacha.v
+ cipher/chacha/src/rtl/chacha_core.v
+ cipher/chacha/src/rtl/chacha_qr.v
+
+[modexpa7]
+block_memory = yes
+error_wire = no
+vfiles =
+ math/modexpa7/src/rtl/dsp_multiplier_a7.v
+ math/modexpa7/src/rtl/dsp_subtractor_a7.v
+ math/modexpa7/src/rtl/modexpa7_adder64_carry32.v
+ math/modexpa7/src/rtl/modexpa7_buffer_core.v
+ math/modexpa7/src/rtl/modexpa7_buffer_user.v
+ math/modexpa7/src/rtl/modexpa7_modinv32.v
+ math/modexpa7/src/rtl/modexpa7_montgomery_coeff.v
+ math/modexpa7/src/rtl/modexpa7_montgomery_multiplier.v
+ math/modexpa7/src/rtl/modexpa7_top.v
+ math/modexpa7/src/rtl/modexpa7_wrapper.v
+ math/modexpa7/src/rtl/ram_1rw_1ro_readfirst.v
+
+[modexp]
+error_wire = no
+vfiles =
+ math/modexp/src/rtl/adder.v
+ math/modexp/src/rtl/blockmem1r1w.v
+ math/modexp/src/rtl/blockmem2r1wptr.v
+ math/modexp/src/rtl/blockmem2r1w.v
+ math/modexp/src/rtl/blockmem2rptr1w.v
+ math/modexp/src/rtl/modexp.v
+ math/modexp/src/rtl/modexp_core.v
+ math/modexp/src/rtl/montprod.v
+ math/modexp/src/rtl/residue.v
+ math/modexp/src/rtl/shl.v
+ math/modexp/src/rtl/shr.v
+
+[mkmif]
+error_wire = no
+vfiles =
+ util/mkmif/src/rtl/mkmif.v
+ util/mkmif/src/rtl/mkmif_core.v
+ util/mkmif/src/rtl/mkmif_spi.v
diff --git a/build/config.py b/build/config.py
new file mode 100755
index 0000000..e737c92
--- /dev/null
+++ b/build/config.py
@@ -0,0 +1,573 @@
+#!/usr/bin/env python
+
+"""
+Generate core_selector.v and core_vfiles.mk for a set of cores.
+"""
+
+#=======================================================================
+# Copyright (c) 2015-2016, NORDUnet A/S All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# - Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# - Neither the name of the NORDUnet nor the names of its contributors may
+# be used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#=======================================================================
+
+# The modexpa7 core drags in a one clock cycle delay to other cores,
+# to compensate for the extra clock cycle consumed by the block
+# memories used in the modexpa7 core. We probably want a general
+# solution for this, because we're going to run into this problem for
+# any core that handles arguments big enough to require block memory.
+
+# To Do:
+#
+# - Consider automating the one-clock-cycle delay stuff by adding
+# another boolean flag to the config file. Default would be no
+# delay, if any included core sets the "I use block memories" flag,
+# all other cores would get the delay. Slightly tedious but
+# something we can calculate easily enough, and probably an
+# improvement over wiring in the delay when nothing needs it.
+#
+# - Rename script and its config file to something more meaningful.
+
+
+def main():
+ """
+ Parse arguments and config file, generate core list, generate output.
+ """
+
+ from argparse import ArgumentParser, FileType, ArgumentDefaultsHelpFormatter
+ from sys import exit
+
+ parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter)
+ parser.add_argument("-d", "--debug", help = "enable debugging", action = "store_true")
+ parser.add_argument("-s", "--section", help = "config file section")
+ parser.add_argument("-c", "--config", help = "configuration file", default = "config.cfg", type = FileType("r"))
+ parser.add_argument("--verilog", help = "verilog output file", default = "core_selector.v", type = FileType("w"))
+ parser.add_argument("--makefile", help = "output makefile", default = "core_vfiles.mk", type = FileType("w"))
+ parser.add_argument("core", help = "name(s) of core(s)", nargs = "*")
+ args = parser.parse_args()
+
+ try:
+ cfg = RawConfigParser()
+ cfg.readfp(args.config)
+
+ if args.core:
+ cores = args.core
+ else:
+ section = args.section or cfg.get("default", "default-section")
+ cores = cfg.get(section, "cores").split()
+
+ cores.insert(0, "board_regs")
+ cores.insert(1, "comm_regs")
+
+ cores = tuple(Core.new(core) for core in cores)
+
+ core_number = 0
+ for core in cores:
+ core_number = core.assign_core_number(core_number)
+
+ for core in cores:
+ core.configure(cfg)
+
+ if False:
+
+ # For some reason, attempting to optimize out the delay
+ # code entirely results in a non-working bitstream. Don't
+ # know why, disabling the optimization works, so just do
+ # that for now.
+
+ Core.need_one_cycle_delay = any(core.block_memory for core in cores)
+
+ args.verilog.write(createModule_template.format(
+ addrs = "".join(core.createAddr() for core in cores),
+ insts = "".join(core.createInstance() for core in cores),
+ muxes = "".join(core.createMux() for core in cores),
+ ports = "".join(core.createPort() for core in cores) ))
+
+ args.makefile.write(listVfiles_template.format(
+ vfiles = "".join(core.listVfiles() for core in cores)))
+
+ except Exception, e:
+ if args.debug:
+ raise
+ exit(str(e))
+
+
+try:
+ import ConfigParser as configparser
+except ImportError:
+ import configparser
+
+class RawConfigParser(configparser.RawConfigParser):
+ """
+ RawConfigParser with a few extensions.
+ """
+
+ def getboolean(self, section, option, default = False):
+ if self.has_option(section, option):
+ # RawConfigParser is an old-stle class, super() doesn't work, feh.
+ return configparser.RawConfigParser.getboolean(self, section, option)
+ else:
+ return default
+
+ def getvalues(self, section, option):
+ if self.has_option(section, option):
+ for value in self.get(section, option).split():
+ yield value
+
+
+class Core(object):
+ """
+ Data and methods for a generic core. We can use this directly for
+ most cores, a few are weird and require subclassing to override
+ particular methods.
+ """
+
+ # Class variable tracking how many times a particular core has
+ # been instantiated. This controls instance numbering.
+
+ _instance_count = {}
+
+ # Class variable mapping core name to subclass for special cases.
+
+ special_class = {}
+
+ # Class variable recording whether we need a one-cycle delay to
+ # compensate for block memories.
+
+ need_one_cycle_delay = True
+
+ def __init__(self, name):
+ self.name = name
+ self.core_number = None
+ self.vfiles = []
+ self.error_wire = True
+ self.block_memory = False
+ self.instance_number = self._instance_count.get(name, 0)
+ self._instance_count[name] = self.instance_number + 1
+
+ @classmethod
+ def new(cls, name):
+ return cls.special_class.get(name, cls)(name)
+
+ def assign_core_number(self, n):
+ self.core_number = n
+ return n + 1
+
+ def configure(self, cfg):
+ if self.instance_number == 0:
+ self.vfiles.extend(cfg.getvalues(self.name, "vfiles"))
+ for required in cfg.getvalues(self.name, "requires"):
+ if required not in self._instance_count:
+ self.vfiles.extend(cfg.getvalues(required, "vfiles"))
+ self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire)
+ self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory)
+
+ @property
+ def instance_name(self):
+ if self._instance_count[self.name] > 1:
+ return "{}_{}".format(self.name, self.instance_number)
+ else:
+ return self.name
+
+ @property
+ def upper_instance_name(self):
+ return self.instance_name.upper()
+
+ @property
+ def reset_pin(self):
+ return ".reset_n(sys_rst_n)"
+
+ @property
+ def error_port(self):
+ return ",\n .error(error_{core.instance_name})".format(core = self) if self.error_wire else ""
+
+ @property
+ def one_cycle_delay(self):
+ return one_cycle_delay_template.format(core = self) if self.need_one_cycle_delay and not self.block_memory else ""
+
+ @property
+ def mux_data_reg(self):
+ return "read_data_" + self.instance_name + ("_reg" if self.need_one_cycle_delay and not self.block_memory else "")
+
+ @property
+ def mux_error_reg(self):
+ return "error_" + self.instance_name if self.error_wire else "0"
+
+ def createInstance(self):
+ return createInstance_template_generic.format(core = self)
+
+ def createAddr(self):
+ return createAddr_template.format(core = self)
+
+ def createMux(self):
+ return createMux_template.format(core = self, core0 = self)
+
+ def createPort(self):
+ return ""
+
+ def listVfiles(self):
+ return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles)
+
+
+class SubCore(Core):
+ """"
+ Override mux handling for TRNG's sub-cores.
+ """
+
+ def __init__(self, name, parent):
+ super(SubCore, self).__init__(name)
+ self.parent = parent
+
+ def createMux(self):
+ return createMux_template.format(core = self, core0 = self.parent)
+
+
+class TRNGCore(Core):
+ """
+ The TRNG core has an internal mux with slots for 15 sub-cores,
+ most of which are empty. This is a bit of a mess.
+
+ Mostly this means that our method calls have to iterate over all
+ of the subcores after handling the base TRNG core, but we also use
+ different templates, and fiddle with addresses a bit.
+
+ Mux numbers have to be dug out of the TRNG Verilog source.
+ """
+
+ # TRNG subcore name -> internal mux number.
+ subcore_parameters = dict(avalanche_entropy = 0x1,
+ rosc_entropy = 0x2,
+ trng_mixer = 0x3,
+ trng_csprng = 0x4)
+
+ def __init__(self, name):
+ super(TRNGCore, self).__init__(name)
+ self.subcores = tuple(SubCore(name, self)
+ for name in sorted(self.subcore_parameters,
+ key = lambda x: self.subcore_parameters[x]))
+
+ def assign_core_number(self, n):
+ n = super(TRNGCore, self).assign_core_number(n)
+ for subcore in self.subcores:
+ subcore.assign_core_number(self.core_number + self.subcore_parameters[subcore.name])
+ return n + 15
+
+ @property
+ def last_subcore_upper_instance_name(self):
+ return self.subcores[-1].upper_instance_name
+
+ def createInstance(self):
+ return createInstance_template_TRNG.format(core = self)
+
+ def createAddr(self):
+ return super(TRNGCore, self).createAddr() + "".join(subcore.createAddr() for subcore in self.subcores)
+
+ def createMux(self):
+ return super(TRNGCore, self).createMux() + "".join(subcore.createMux() for subcore in self.subcores)
+
+
+class ModExpA7Core(Core):
+ """
+ ModExpA7 core consumes as much space as four ordinary cores, and
+ uses different templates to handle the differences in timing and
+ addressing.
+ """
+
+ def assign_core_number(self, n):
+ n = super(ModExpA7Core, self).assign_core_number(n)
+ return n + 3
+
+ def createInstance(self):
+ return createInstance_template_ModExpA7.format(core = self)
+
+ def createMux(self):
+ return createMux_modexpa7_template.format(core = self, core0 = self)
+
+class MkmifCore(Core):
+ """
+ MKM interface core has extra ports for the SPI signal lines.
+ """
+
+ def createPort(self):
+ return """ \
+
+ output wire mkm_sclk,
+ output wire mkm_cs_n,
+ input wire mkm_do,
+ output wire mkm_di,
+ """
+
+ def createInstance(self):
+ return createInstance_template_MKMIF.format(core = self)
+
+# Hook special classes in as handlers for the cores that require them.
+
+Core.special_class.update(
+ trng = TRNGCore,
+ modexpa7 = ModExpA7Core,
+ mkmif = MkmifCore)
+
+
+# Templates (format strings), here instead of inline in the functions
+# that use them, both because some of these are shared between
+# multiple functions and because it's easier to read these (and get
+# the indentation right) when the're separate.
+
+# Template used by .createAddr() methods.
+
+createAddr_template = """\
+ localparam CORE_ADDR_{core.upper_instance_name:21s} = 15'h{core.core_number:02x};
+"""
+
+# Template used by Core.createInstance().
+
+createInstance_template_generic = """\
+ //----------------------------------------------------------------
+ // {core.upper_instance_name}
+ //----------------------------------------------------------------
+ wire enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
+ wire [31: 0] read_data_{core.instance_name};
+ wire error_{core.instance_name};
+
+ {core.name} {core.instance_name}_inst
+ (
+ .clk(sys_clk),
+ {core.reset_pin},
+
+ .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
+ .we(sys_fmc_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_{core.instance_name}){core.error_port}
+ );
+
+{core.one_cycle_delay}
+
+"""
+
+# Template used by ModExpA7Core.createInstance(). This is different
+# enough from the base template that it's easier to make this separate.
+
+createInstance_template_ModExpA7 = """\
+ //----------------------------------------------------------------
+ // {core.upper_instance_name}
+ //----------------------------------------------------------------
+ wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 15'h03);
+ wire [31: 0] read_data_{core.instance_name};
+ wire [1:0] {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name};
+
+ {core.name}_wrapper {core.instance_name}_inst
+ (
+ .clk(sys_clk),
+ {core.reset_pin},
+
+ .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
+ .we(sys_fmc_wr),
+
+ .address({{{core.instance_name}_prefix, addr_core_reg}}),
+ .write_data(sys_write_data),
+ .read_data(read_data_{core.instance_name})
+ );
+
+
+"""
+
+# Template used by TRNGCore.createInstance(); this is different enough
+# from the generic template that it's (probably) clearer to have this
+# separate.
+
+createInstance_template_TRNG = """\
+ //----------------------------------------------------------------
+ // {core.upper_instance_name}
+ //----------------------------------------------------------------
+ wire enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 15'h0f);
+ wire [31: 0] read_data_{core.instance_name};
+ wire error_{core.instance_name};
+ wire [3:0] {core.instance_name}_prefix = addr_core_num[3:0] - CORE_ADDR_{core.upper_instance_name};
+
+ {core.name} {core.instance_name}_inst
+ (
+ .clk(sys_clk),
+ {core.reset_pin},
+
+ .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
+ .we(sys_fmc_wr),
+
+ .address({{{core.instance_name}_prefix, addr_core_reg}}),
+ .write_data(sys_write_data),
+ .read_data(read_data_{core.instance_name}),
+ .error(error_{core.instance_name}),
+
+ .avalanche_noise(noise),
+ .debug(debug)
+ );
+
+{core.one_cycle_delay}
+
+"""
+
+# Template used by Mkmif.createInstance(). This is different
+# enough from the base template that it's easier to make this separate.
+
+createInstance_template_MKMIF = """\
+ //----------------------------------------------------------------
+ // {core.upper_instance_name}
+ //----------------------------------------------------------------
+ wire enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
+ wire [31: 0] read_data_{core.instance_name};
+
+ {core.name} {core.instance_name}_inst
+ (
+ .clk(sys_clk),
+ {core.reset_pin},
+
+ .spi_sclk(mkm_sclk),
+ .spi_cs_n(mkm_cs_n),
+ .spi_do(mkm_do),
+ .spi_di(mkm_di),
+
+ .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
+ .we(sys_fmc_wr),
+
+ .address(addr_core_reg),
+ .write_data(sys_write_data),
+ .read_data(read_data_{core.instance_name}){core.error_port}
+ );
+
+{core.one_cycle_delay}
+
+"""
+
+# Template for one-cycle delay code.
+
+one_cycle_delay_template = """\
+ reg [31: 0] read_data_{core.instance_name}_reg;
+ always @(posedge sys_clk)
+ read_data_{core.instance_name}_reg <= read_data_{core.instance_name};
+"""
+
+# Template for .createMux() methods.
+
+createMux_template = """\
+ CORE_ADDR_{core.upper_instance_name}:
+ begin
+ sys_read_data_mux = {core0.mux_data_reg};
+ sys_error_mux = {core0.mux_error_reg};
+ end
+"""
+
+# Template for ModExpA7.createMux() method.
+
+createMux_modexpa7_template = """\
+ CORE_ADDR_{core.upper_instance_name} + 0,
+ CORE_ADDR_{core.upper_instance_name} + 1,
+ CORE_ADDR_{core.upper_instance_name} + 2,
+ CORE_ADDR_{core.upper_instance_name} + 3:
+ begin
+ sys_read_data_mux = {core0.mux_data_reg};
+ sys_error_mux = {core0.mux_error_reg};
+ end
+"""
+
+
+# Top-level (createModule) template.
+
+createModule_template = """\
+// NOTE: This file is generated; do not edit by hand.
+
+module core_selector
+ (
+ input wire sys_clk,
+ input wire sys_rst_n,
+
+ input wire [23: 0] sys_fmc_addr,
+ input wire sys_fmc_wr,
+ input wire sys_fmc_rd,
+ output wire [31: 0] sys_read_data,
+ input wire [31: 0] sys_write_data,
+ output wire sys_error,
+{ports}
+ input wire noise,
+ output wire [7 : 0] debug
+ );
+
+
+ //----------------------------------------------------------------
+ // Address Decoder
+ //----------------------------------------------------------------
+ // upper 15 bits specify core being addressed
+ wire [14: 0] addr_core_num = sys_fmc_addr[23: 8];
+ // lower 8 bits specify register offset in core
+ wire [ 7: 0] addr_core_reg = sys_fmc_addr[ 7: 0];
+
+
+ //----------------------------------------------------------------
+ // Core Address Table
+ //----------------------------------------------------------------
+{addrs}
+
+{insts}
+ //----------------------------------------------------------------
+ // Output (Read Data) Multiplexer
+ //----------------------------------------------------------------
+ reg [31: 0] sys_read_data_mux;
+ assign sys_read_data = sys_read_data_mux;
+ reg sys_error_mux;
+ assign sys_error = sys_error_mux;
+
+ always @*
+
+ case (addr_core_num)
+{muxes}
+ default:
+ begin
+ sys_read_data_mux = {{32{{1'b0}}}};
+ sys_error_mux = 1;
+ end
+ endcase
+
+
+endmodule
+
+
+//======================================================================
+// EOF core_selector.v
+//======================================================================
+"""
+
+# Template for makefile snippet listing Verilog source files.
+
+listVfiles_template = """\
+# NOTE: This file is generated; do not edit by hand.
+
+vfiles +={vfiles}
+"""
+
+# Run main program.
+
+if __name__ == "__main__":
+ main()
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 6410d44..79bfba8 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -235,9 +235,9 @@ module alpha_fmc_top
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
- .sys_eim_addr(sys_fmc_addr[16:0]), // XXX parameterize
- .sys_eim_wr(sys_fmc_wren),
- .sys_eim_rd(sys_fmc_rden),
+ .sys_fmc_addr(sys_fmc_addr),
+ .sys_fmc_wr(sys_fmc_wren),
+ .sys_fmc_rd(sys_fmc_rden),
.sys_write_data(sys_fmc_dout),
.sys_read_data(sys_fmc_din),
--
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