[Cryptech-Commits] [user/ft/alpha_to_kicad] 05/09: via size and micro fixups

git at cryptech.is git at cryptech.is
Sun Dec 11 21:22:29 UTC 2016


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fredrik at thulin.net pushed a commit to branch master
in repository user/ft/alpha_to_kicad.

commit c824618371135d0b50835af0d8a5225523515bb8
Author: Fredrik Thulin <fredrik at thulin.net>
AuthorDate: Thu Oct 20 15:20:12 2016 +0200

    via size and micro fixups
---
 rev03-KiCad/Cryptech Alpha.kicad_pcb | 7544 +++++++++++++++++-----------------
 1 file changed, 3772 insertions(+), 3772 deletions(-)

diff --git a/rev03-KiCad/Cryptech Alpha.kicad_pcb b/rev03-KiCad/Cryptech Alpha.kicad_pcb
index f9c9232..0146ef1 100644
--- a/rev03-KiCad/Cryptech Alpha.kicad_pcb	
+++ b/rev03-KiCad/Cryptech Alpha.kicad_pcb	
@@ -3,7 +3,7 @@
   (general
     (links 1412)
     (no_connects 695)
-    (area -32.294113 -104.25 148.466654 54.64848)
+    (area -32.294113 -104.250001 148.466654 54.64848)
     (thickness 1.6)
     (drawings 7054)
     (tracks 9335)
@@ -15,12 +15,12 @@
   (page A4)
   (layers
     (0 F.Cu signal)
-    (1 In1.Cu signal)
-    (2 In2.Cu signal)
-    (3 In3.Cu signal)
-    (4 In4.Cu signal)
+    (1 In1.Cu power)
+    (2 In2.Cu mixed)
+    (3 In3.Cu power)
+    (4 In4.Cu power)
     (5 In5.Cu signal)
-    (6 In6.Cu signal)
+    (6 In6.Cu power)
     (31 B.Cu signal)
     (32 B.Adhes user)
     (33 F.Adhes user)
@@ -56,8 +56,8 @@
     (via_min_drill 0.508)
     (uvia_size 0.508)
     (uvia_drill 0.127)
-    (uvias_allowed no)
-    (uvia_min_size 0.508)
+    (uvias_allowed yes)
+    (uvia_min_size 0.5)
     (uvia_min_drill 0.127)
     (pcb_text_width 0.3)
     (pcb_text_size 1.5 1.5)
@@ -748,25 +748,25 @@
     (fp_text value "Connector; Header; 10 Position" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 18 AVR_GPIO_1))
-    (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 24 AVR_GPIO_7))
-    (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 23 AVR_GPIO_6))
-    (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 22 AVR_GPIO_5))
-    (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 21 AVR_GPIO_4))
-    (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 20 AVR_GPIO_3))
-    (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 19 AVR_GPIO_2))
-    (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 17 AVR_GPIO_0))
-    (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
   )
 
@@ -780,9 +780,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 0 1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 0 -1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 211 MKM_AVR_MISO))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl
       (at (xyz 0 0 0))
@@ -864,9 +864,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 283 PWR_18V))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -885,9 +885,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 224 NetC5_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -906,9 +906,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 301 VCC_5V0))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -927,9 +927,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 283 PWR_18V))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -1011,9 +1011,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 5 15V_STABLE))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 225 NetC11_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1032,9 +1032,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 226 NetC12_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1053,9 +1053,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 5 15V_STABLE))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -1074,9 +1074,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 275 NOISE_IN))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1095,9 +1095,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 287 RAW_NOISE))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 7 NetC15_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1116,9 +1116,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1137,9 +1137,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 227 NetC17_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1158,9 +1158,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 279 OSC_OUT))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1179,9 +1179,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1200,9 +1200,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 277 NRST))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1326,9 +1326,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -1347,9 +1347,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -1368,9 +1368,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1389,9 +1389,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1410,9 +1410,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -1431,9 +1431,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
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+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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@@ -1998,9 +1998,9 @@
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2019,9 +2019,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2040,9 +2040,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2061,9 +2061,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2082,9 +2082,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2103,9 +2103,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2124,9 +2124,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2145,9 +2145,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2166,9 +2166,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2187,9 +2187,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2208,9 +2208,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2229,9 +2229,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2250,9 +2250,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 228 NetC70_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2271,9 +2271,9 @@
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 229 NetC71_2))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2292,9 +2292,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 205 FT_VREGIN))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -2313,9 +2313,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 205 FT_VREGIN))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2334,9 +2334,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 202 FT_VCCORE))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2355,9 +2355,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 230 NetC75_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2376,9 +2376,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 200 FT_VCCA))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2397,9 +2397,9 @@
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 203 FT_VPHY))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -2418,9 +2418,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 231 NetC78_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2439,9 +2439,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 203 FT_VPHY))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2460,9 +2460,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 204 FT_VPLL))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -2481,9 +2481,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 204 FT_VPLL))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2502,9 +2502,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
-    (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -2523,9 +2523,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2544,9 +2544,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2565,9 +2565,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2586,9 +2586,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2607,9 +2607,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
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-    (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers B.Cu B.Paste B.Mask)
       (net 188 FT_MGMT_VREGIN))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -2628,9 +2628,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 188 FT_MGMT_VREGIN))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2649,9 +2649,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 201 FT_VCCORE1))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2670,9 +2670,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 232 NetC90_2))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2691,9 +2691,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 199 FT_VCCA1))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2712,9 +2712,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 186 FT_MGMT_VPHY))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -2733,9 +2733,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 233 NetC93_2))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2754,9 +2754,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 186 FT_MGMT_VPHY))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2775,9 +2775,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 187 FT_MGMT_VPLL))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -2796,9 +2796,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 187 FT_MGMT_VPLL))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -2817,9 +2817,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -2838,9 +2838,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2859,9 +2859,9 @@
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2880,9 +2880,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2901,9 +2901,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2922,9 +2922,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -2943,9 +2943,9 @@
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2964,9 +2964,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -2985,9 +2985,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3006,9 +3006,9 @@
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3027,9 +3027,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 3 3V3_BATT))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3048,9 +3048,9 @@
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3069,9 +3069,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3090,9 +3090,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3111,9 +3111,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3132,9 +3132,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3195,9 +3195,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 234 NetC115_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3216,9 +3216,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 235 NetC116_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3237,9 +3237,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 236 NetC117_1))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 237 NetC117_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 239 NetC118_2))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 238 NetC118_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3342,9 +3342,9 @@
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3384,9 +3384,9 @@
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3510,9 +3510,9 @@
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3531,9 +3531,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3552,9 +3552,9 @@
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-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -3594,9 +3594,9 @@
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3615,9 +3615,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3636,9 +3636,9 @@
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-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -3678,9 +3678,9 @@
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3699,9 +3699,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -3720,9 +3720,9 @@
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-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -3741,9 +3741,9 @@
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -3762,9 +3762,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -3783,9 +3783,9 @@
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3804,9 +3804,9 @@
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-    (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -3825,9 +3825,9 @@
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -3846,9 +3846,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
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@@ -3867,9 +3867,9 @@
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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@@ -3888,9 +3888,9 @@
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-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
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@@ -3909,9 +3909,9 @@
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-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
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     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -3930,9 +3930,9 @@
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3951,9 +3951,9 @@
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -3972,9 +3972,9 @@
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+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
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     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
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+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
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-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
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-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
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+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
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+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
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+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4224,9 +4224,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 175 FPGA_VCCINT_1V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4350,9 +4350,9 @@
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-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4392,9 +4392,9 @@
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4413,9 +4413,9 @@
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-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4434,9 +4434,9 @@
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-    (pad 1 smd rect (at 1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -1 0 180) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4455,9 +4455,9 @@
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+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4476,9 +4476,9 @@
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-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4497,9 +4497,9 @@
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-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
       (at (xyz 0 0 0))
@@ -4518,9 +4518,9 @@
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-    (pad 1 smd rect (at 0 1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -1 90) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -1 90) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4539,9 +4539,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0 1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -1 270) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -1 270) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4560,9 +4560,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 1 smd rect (at -1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 1 0) (size 1.000001 1.2) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 1 0) (size 1 1.2) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/68E8DA21-73BF.wrl
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@@ -4581,9 +4581,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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     (fp_text value "" (at 0 0) (layer F.SilkS) hide
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4623,9 +4623,9 @@
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4749,9 +4749,9 @@
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+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4791,9 +4791,9 @@
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4833,9 +4833,9 @@
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-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4854,9 +4854,9 @@
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
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@@ -4875,9 +4875,9 @@
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4896,9 +4896,9 @@
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4917,9 +4917,9 @@
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-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4938,9 +4938,9 @@
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-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4959,9 +4959,9 @@
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -4980,9 +4980,9 @@
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-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -5001,9 +5001,9 @@
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-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -5022,9 +5022,9 @@
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
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@@ -5043,9 +5043,9 @@
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5064,9 +5064,9 @@
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+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5127,9 +5127,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 240 NetC207_1))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5148,9 +5148,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 242 NetC208_2))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 241 NetC208_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5211,9 +5211,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 285 PWR_ENA_VCCINT))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5232,9 +5232,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 286 PWR_ENA_VCCO))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5253,9 +5253,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 284 PWR_ENA_VCCAUX))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5274,9 +5274,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 205 FT_VREGIN))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5295,9 +5295,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 188 FT_MGMT_VREGIN))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/ECAF1ED8-FCC0.wrl
       (at (xyz 0 0 0))
@@ -5324,14 +5324,14 @@
       (net 6 GND))
     (pad GND smd rect (at -4.34 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad GND smd rect (at 1.6002 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad ID smd rect (at 0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask))
-    (pad D+ smd rect (at 0 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask))
+    (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 41 D1_P))
-    (pad D- smd rect (at -0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 40 D1_N))
-    (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 205 FT_VREGIN))
     (pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
@@ -5356,14 +5356,14 @@
     (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask))
     (pad GND smd rect (at -4.34 -3.5052) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 188 FT_MGMT_VREGIN))
-    (pad D- smd rect (at -0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 2 DM_N))
-    (pad D+ smd rect (at 0 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 1 DM_P))
-    (pad ID smd rect (at 0.8 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask))
-    (pad GND smd rect (at 1.6002 -3.7 180) (size 0.599999 1.599999) (layers F.Cu F.Paste F.Mask)
+    (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask))
+    (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.599999) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (pad GND smd rect (at -4.34 2) (size 1.599999 2.000001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
@@ -5476,9 +5476,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
-    (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 203 FT_VPHY))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
       (at (xyz 0 0 0))
@@ -5497,9 +5497,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.85 0 90) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.85 0 90) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 204 FT_VPLL))
-    (pad 1 smd rect (at -0.85 0 90) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.85 0 90) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
       (at (xyz 0 0 0))
@@ -5518,9 +5518,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
-    (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 186 FT_MGMT_VPHY))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
       (at (xyz 0 0 0))
@@ -5539,9 +5539,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 187 FT_MGMT_VPLL))
-    (pad 1 smd rect (at 0 -0.85) (size 1.000001 0.900001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.85) (size 1 0.900001) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/AF13F747-700F.wrl
       (at (xyz 0 0 0))
@@ -5831,16 +5831,16 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask))
-    (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask))
+    (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 277 NRST))
-    (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 294 SWDIO))
-    (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 293 SWDCLK))
-    (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/670BFB14-85C2.wrl
       (at (xyz 0 0 0))
@@ -5859,17 +5859,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 205 FT_VREGIN))
-    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 298 USB_P))
-    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 297 USB_N))
-    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 194 FT_RXD1))
-    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 196 FT_TXD1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -5888,17 +5888,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 183 FT_MGMT_TXD1))
-    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 181 FT_MGMT_RXD1))
-    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 295 USB_MGMT_N))
-    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 296 USB_MGMT_P))
-    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 188 FT_MGMT_VREGIN))
-    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -5940,9 +5940,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 244 NetJP2_2))
-    (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 4 15V_LDO_ENABLE))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/3416A7AC-A52A.wrl
       (at (xyz 0 0 0))
@@ -5961,17 +5961,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 211 MKM_AVR_MISO))
-    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 3 3V3_BATT))
-    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 213 MKM_AVR_SCK))
-    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 212 MKM_AVR_MOSI))
-    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 38 AVR_RESET))
-    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -5990,11 +5990,11 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 3 3V3_BATT))
-    (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/836C6F64-A2E5.wrl
       (at (xyz 0 0 0))
@@ -6013,17 +6013,17 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 121 FPGA_CFG_CTRL_ARM_ENA))
-    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 291 SPI_A_TRISTATE))
-    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 122 FPGA_CFG_CTRL_FPGA_DIS))
-    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 292 SPI_B_TRISTATE))
-    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 173 FPGA_PROM_W_N))
-    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B3089A96-FA19.wrl
       (at (xyz 0 0 0))
@@ -6042,9 +6042,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 245 NetLED1_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6063,9 +6063,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 246 NetLED2_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6084,9 +6084,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 247 NetLED3_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6105,9 +6105,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 248 NetLED4_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6126,9 +6126,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 249 NetLED9_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6147,9 +6147,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 250 NetLED10_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6168,9 +6168,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 251 NetLED11_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6189,9 +6189,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 252 NetLED12_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6210,9 +6210,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 253 NetLED13_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 129 FPGA_DONE_INT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6231,9 +6231,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 254 NetLED14_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6252,9 +6252,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 255 NetLED15_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6273,9 +6273,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 256 NetLED16_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6294,9 +6294,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 257 NetLED17_1))
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6315,9 +6315,9 @@
     (fp_text value "Chip, 2-Leads, Body 1,6x0,8mm, IPC Medium Density" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 259 NetLED18_2))
-    (pad 1 smd rect (at 0 -0.8) (size 1.000001 0.800001) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.8) (size 1 0.800001) (layers F.Cu F.Paste F.Mask)
       (net 258 NetLED18_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A9F03225-78F3.wrl
       (at (xyz 0 0 0))
@@ -6467,9 +6467,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 283 PWR_18V))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 263 NetR1_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6488,9 +6488,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 263 NetR1_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6509,9 +6509,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 264 NetR3_2))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 263 NetR1_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6530,9 +6530,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 132 FPGA_GCLK))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 262 NetQ5_3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6551,9 +6551,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 260 NetQ1_1))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 131 FPGA_ENTROPY_DISABLE))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6572,9 +6572,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 260 NetQ1_1))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6593,9 +6593,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 4 15V_LDO_ENABLE))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 283 PWR_18V))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6614,9 +6614,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 265 NetR8_1))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 301 VCC_5V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6635,9 +6635,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 265 NetR8_1))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6656,9 +6656,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 287 RAW_NOISE))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 275 NOISE_IN))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6677,9 +6677,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 287 RAW_NOISE))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 5 15V_STABLE))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6698,9 +6698,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 7 NetC15_2))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 8 AMPLIFIED))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6719,9 +6719,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 8 AMPLIFIED))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6740,9 +6740,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 278 OSC_IN))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 227 NetC17_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6761,9 +6761,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 39 BOOT0))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6782,9 +6782,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 248 NetLED4_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 15 ARM_LED3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6803,9 +6803,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 243 NetIC1_3))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6824,9 +6824,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 206 KSM_PROM_CS_N))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6845,9 +6845,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 290 RTC_SDA))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6866,9 +6866,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 289 RTC_SCL))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6887,9 +6887,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 288 RTC_MFP))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6908,9 +6908,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 190 FT_REF))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6929,9 +6929,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 198 FT_VCC3V3))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 192 FT_RESET))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6950,9 +6950,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 189 FT_REF1))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6971,9 +6971,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 185 FT_MGMT_VCC3V3))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 191 FT_RESET1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -6992,9 +6992,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 38 AVR_RESET))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7013,9 +7013,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 35 AVR_LED3))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 252 NetLED12_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7034,9 +7034,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 266 NetR32_2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7055,9 +7055,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 267 NetR33_2))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 3 3V3_BATT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7076,9 +7076,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 216 MKM_CS_N))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 3 3V3_BATT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7097,9 +7097,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 253 NetLED13_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7118,9 +7118,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 130 FPGA_DONE))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 129 FPGA_DONE_INT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7139,9 +7139,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 154 FPGA_INIT_B_INT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7160,9 +7160,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 168 FPGA_PROGRAM_B))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7181,9 +7181,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 155 FPGA_INIT_B))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7202,9 +7202,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 161 FPGA_JTAG_TDI))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7223,9 +7223,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 163 FPGA_JTAG_TMS))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7244,9 +7244,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 160 FPGA_JTAG_TCK))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7265,9 +7265,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 291 SPI_A_TRISTATE))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7286,9 +7286,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 292 SPI_B_TRISTATE))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7307,9 +7307,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 261 NetQ5_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7328,9 +7328,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 173 FPGA_PROM_W_N))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7349,9 +7349,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 169 FPGA_PROM_CS_N))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7370,9 +7370,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 268 NetR52_1))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 301 VCC_5V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7391,9 +7391,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
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-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 269 NetR53_2))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7412,9 +7412,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
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-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 270 NetR54_1))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 301 VCC_5V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7433,9 +7433,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 271 NetR55_2))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7454,9 +7454,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 237 NetC117_2))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 236 NetC117_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7475,9 +7475,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 237 NetC117_2))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7496,9 +7496,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 239 NetC118_2))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 238 NetC118_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7517,9 +7517,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 239 NetC118_2))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7538,9 +7538,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 236 NetC117_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7559,9 +7559,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 238 NetC118_1))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7580,9 +7580,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 154 FPGA_INIT_B_INT))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 153 FPGA_INIT_B_INT1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7601,9 +7601,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 167 FPGA_PROGRAM_B1))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 168 FPGA_PROGRAM_B))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7622,9 +7622,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 255 NetLED15_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 150 FPGA_GPIO_LED_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7643,9 +7643,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 272 NetR65_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7664,9 +7664,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 273 NetR66_1))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 301 VCC_5V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7685,9 +7685,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 241 NetC208_1))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 274 NetR67_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7706,9 +7706,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 242 NetC208_2))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 241 NetC208_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7727,9 +7727,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 242 NetC208_2))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7748,9 +7748,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 241 NetC208_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7769,9 +7769,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 127 FPGA_CFG_SCLK1))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 128 FPGA_CFG_SCLK))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7790,9 +7790,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 301 VCC_5V0))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 285 PWR_ENA_VCCINT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7811,9 +7811,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 301 VCC_5V0))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 280 POK_VCCAUX))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7832,9 +7832,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 280 POK_VCCAUX))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 286 PWR_ENA_VCCO))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7853,9 +7853,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 301 VCC_5V0))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 281 POK_VCCINT))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7874,9 +7874,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 281 POK_VCCINT))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 284 PWR_ENA_VCCAUX))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7895,9 +7895,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 301 VCC_5V0))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 282 POK_VCCO))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7916,9 +7916,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 258 NetLED18_1))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 301 VCC_5V0))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7937,9 +7937,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 3 3V3_BATT))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 214 MKM_CONTROL_AVR_ENA))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7958,9 +7958,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 215 MKM_CONTROL_FPGA_DIS))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -7979,9 +7979,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 3 3V3_BATT))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 37 AVR_PANIC))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8000,9 +8000,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 126 FPGA_CFG_MOSI))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 125 FPGA_CFG_MOSI1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8021,9 +8021,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 123 FPGA_CFG_MISO1))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 124 FPGA_CFG_MISO))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8042,9 +8042,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 120 FPGA_CFG_CS_N))
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 119 FPGA_CFG_CS_N1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8063,9 +8063,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 196 FT_TXD1))
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 197 FT_TXD))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8084,9 +8084,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 -0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 -0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 195 FT_RXD))
-    (pad 2 smd rect (at 0 0.5 270) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 0.5 270) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 194 FT_RXD1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8105,9 +8105,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 183 FT_MGMT_TXD1))
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 184 FT_MGMT_TXD))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8126,9 +8126,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 182 FT_MGMT_RXD))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 181 FT_MGMT_RXD1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8147,9 +8147,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 184 FT_MGMT_TXD))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8168,9 +8168,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 197 FT_TXD))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8189,9 +8189,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 14 ARM_LED2))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 245 NetLED1_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8210,9 +8210,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 247 NetLED3_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 13 ARM_LED1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8231,9 +8231,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 16 ARM_LED4))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 246 NetLED2_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8252,9 +8252,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 249 NetLED9_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 34 AVR_LED2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8273,9 +8273,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 33 AVR_LED1))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 251 NetLED11_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8294,9 +8294,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 250 NetLED10_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 36 AVR_LED4))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8315,9 +8315,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 151 FPGA_GPIO_LED_2))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 256 NetLED16_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8336,9 +8336,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 254 NetLED14_1))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 152 FPGA_GPIO_LED_3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8357,9 +8357,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 149 FPGA_GPIO_LED_0))
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask)
       (net 257 NetLED17_1))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -8422,9 +8422,9 @@
     (fp_text value TACTILE_SWITCH (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.449999) (layers F.Cu F.Paste F.Mask)
+    (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.449999) (layers F.Cu F.Paste F.Mask)
+    (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
@@ -8445,21 +8445,21 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
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-    (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 160 FPGA_JTAG_TCK))
-    (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 163 FPGA_JTAG_TMS))
-    (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 161 FPGA_JTAG_TDI))
-    (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 162 FPGA_JTAG_TDO))
-    (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/A962434E-CFE5.wrl
       (at (xyz 0 0 0))
@@ -8478,37 +8478,37 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 140 FPGA_GPIO_A_7))
-    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 139 FPGA_GPIO_A_6))
-    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 138 FPGA_GPIO_A_5))
-    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 137 FPGA_GPIO_A_4))
-    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 136 FPGA_GPIO_A_3))
-    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 135 FPGA_GPIO_A_2))
-    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 134 FPGA_GPIO_A_1))
-    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 133 FPGA_GPIO_A_0))
-    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl
       (at (xyz 0 0 0))
@@ -8527,37 +8527,37 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 302 VCCO_3V3))
-    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 141 FPGA_GPIO_B_0))
-    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 142 FPGA_GPIO_B_1))
-    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 143 FPGA_GPIO_B_2))
-    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 144 FPGA_GPIO_B_3))
-    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 6 GND))
-    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 145 FPGA_GPIO_B_4))
-    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 146 FPGA_GPIO_B_5))
-    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 147 FPGA_GPIO_B_6))
-    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1.000001) (layers *.Cu *.Paste *.Mask)
+    (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)
       (net 148 FPGA_GPIO_B_7))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/B280C847-2543.wrl
       (at (xyz 0 0 0))
@@ -9488,21 +9488,21 @@
     (fp_text value SOIC127P600X175-8N (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 8 smd rect (at 2.6924 -1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 8 smd rect (at 2.6924 -1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
-    (pad 7 smd rect (at 2.6924 -0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 7 smd rect (at 2.6924 -0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 288 RTC_MFP))
-    (pad 6 smd rect (at 2.6924 0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 6 smd rect (at 2.6924 0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 289 RTC_SCL))
-    (pad 5 smd rect (at 2.6924 1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 5 smd rect (at 2.6924 1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 290 RTC_SDA))
-    (pad 4 smd rect (at -2.7178 1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 4 smd rect (at -2.7178 1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 3 smd rect (at -2.7178 0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 3 smd rect (at -2.7178 0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 3 3V3_BATT))
-    (pad 2 smd rect (at -2.7178 -0.635) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -2.7178 -0.635) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 229 NetC71_2))
-    (pad 1 smd rect (at -2.7178 -1.905) (size 1.549999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -2.7178 -1.905) (size 1.549999 0.6) (layers F.Cu F.Paste F.Mask)
       (net 228 NetC70_2))
   )
 
@@ -9791,20 +9791,20 @@
     (fp_text value SOIC127P600X175-8N (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 216 MKM_CS_N))
-    (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 221 MKM_MISO))
-    (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask))
-    (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask))
+    (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad 5 smd rect (at 1.905 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 5 smd rect (at 1.905 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 222 MKM_MOSI))
-    (pad 6 smd rect (at 0.635 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 6 smd rect (at 0.635 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 223 MKM_SCK))
-    (pad 7 smd rect (at -0.635 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 7 smd rect (at -0.635 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 267 NetR33_2))
-    (pad 8 smd rect (at -1.905 2.6924 270) (size 1.549999 0.599999) (layers B.Cu B.Paste B.Mask)
+    (pad 8 smd rect (at -1.905 2.6924 270) (size 1.549999 0.6) (layers B.Cu B.Paste B.Mask)
       (net 3 3V3_BATT))
   )
 
@@ -9818,758 +9818,758 @@
     (fp_text value "BGA, 484-Leads, Body 23,00x23,00mmx2,54mm, Pitch 1,00mm" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad AB22 smd circle (at -10.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 63 FMC_A20))
-    (pad AB21 smd circle (at -9.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 62 FMC_A19))
-    (pad AB20 smd circle (at -8.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 64 FMC_A21))
-    (pad AB19 smd circle (at -7.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad AB18 smd circle (at -6.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 67 FMC_A24))
-    (pad AB17 smd circle (at -5.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 47 FMC_A4))
-    (pad AB16 smd circle (at -4.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 44 FMC_A1))
-    (pad AB15 smd circle (at -3.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 51 FMC_A8))
-    (pad AB14 smd circle (at -2.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad AB13 smd circle (at -1.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 49 FMC_A6))
-    (pad AB12 smd circle (at -0.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 57 FMC_A14))
-    (pad AB11 smd circle (at 0.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 74 FMC_D4))
-    (pad AB10 smd circle (at 1.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 55 FMC_A12))
-    (pad AB9 smd circle (at 2.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad AB8 smd circle (at 3.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 58 FMC_A15))
-    (pad AB7 smd circle (at 4.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 70 FMC_D0))
-    (pad AB6 smd circle (at 5.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 71 FMC_D1))
-    (pad AB5 smd circle (at 6.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 90 FMC_D20))
-    (pad AB4 smd circle (at 7.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad AB3 smd circle (at 8.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 86 FMC_D16))
-    (pad AB2 smd circle (at 9.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 85 FMC_D15))
-    (pad AB1 smd circle (at 10.5 10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 84 FMC_D14))
-    (pad AA22 smd circle (at -10.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad AA21 smd circle (at -9.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 79 FMC_D9))
-    (pad AA20 smd circle (at -8.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 152 FPGA_GPIO_LED_3))
-    (pad AA19 smd circle (at -7.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 68 FMC_A25))
-    (pad AA18 smd circle (at -6.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad AA17 smd circle (at -5.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad AA16 smd circle (at -4.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 45 FMC_A2))
-    (pad AA15 smd circle (at -3.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 50 FMC_A7))
-    (pad AA14 smd circle (at -2.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 53 FMC_A10))
-    (pad AA13 smd circle (at -1.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 48 FMC_A5))
-    (pad AA12 smd circle (at -0.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad AA11 smd circle (at 0.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 75 FMC_D5))
-    (pad AA10 smd circle (at 1.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad AA9 smd circle (at 2.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 59 FMC_A16))
-    (pad AA8 smd circle (at 3.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 60 FMC_A17))
-    (pad AA7 smd circle (at 4.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad AA6 smd circle (at 5.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 110 FMC_NWE))
-    (pad AA5 smd circle (at 6.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 89 FMC_D19))
-    (pad AA4 smd circle (at 7.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 92 FMC_D22))
-    (pad AA3 smd circle (at 8.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 88 FMC_D18))
-    (pad AA2 smd circle (at 9.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad AA1 smd circle (at 10.5 9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 83 FMC_D13))
-    (pad Y22 smd circle (at -10.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 66 FMC_A23))
-    (pad Y21 smd circle (at -9.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 65 FMC_A22))
-    (pad Y20 smd circle (at -8.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad Y19 smd circle (at -7.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad Y18 smd circle (at -6.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 78 FMC_D8))
-    (pad Y17 smd circle (at -5.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 43 FMC_A0))
-    (pad Y16 smd circle (at -4.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 46 FMC_A3))
-    (pad Y15 smd circle (at -3.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad Y14 smd circle (at -2.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 54 FMC_A11))
-    (pad Y13 smd circle (at -1.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 52 FMC_A9))
-    (pad Y12 smd circle (at -0.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 77 FMC_D7))
-    (pad Y11 smd circle (at 0.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 76 FMC_D6))
-    (pad Y10 smd circle (at 1.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad Y9 smd circle (at 2.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad Y8 smd circle (at 3.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad Y7 smd circle (at 4.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 61 FMC_A18))
-    (pad Y6 smd circle (at 5.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 109 FMC_NWAIT))
-    (pad Y5 smd circle (at 6.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad Y4 smd circle (at 7.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 91 FMC_D21))
-    (pad Y3 smd circle (at 8.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 87 FMC_D17))
-    (pad Y2 smd circle (at 9.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad Y1 smd circle (at 10.5 8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 218 MKM_FPGA_MISO))
-    (pad W22 smd circle (at -10.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 151 FPGA_GPIO_LED_2))
-    (pad W21 smd circle (at -9.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W20 smd circle (at -8.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 80 FMC_D10))
-    (pad W19 smd circle (at -7.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 42 DIGITIZED_NOISE))
-    (pad W18 smd circle (at -6.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad W17 smd circle (at -5.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 107 FMC_NL))
-    (pad W16 smd circle (at -4.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 108 FMC_NOE))
-    (pad W15 smd circle (at -3.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W14 smd circle (at -2.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 97 FMC_D27))
-    (pad W13 smd circle (at -1.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad W12 smd circle (at -0.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 96 FMC_D26))
-    (pad W11 smd circle (at 0.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 69 FMC_CLK))
-    (pad W10 smd circle (at 1.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 94 FMC_D24))
-    (pad W9 smd circle (at 2.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W8 smd circle (at 3.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad W7 smd circle (at 4.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W6 smd circle (at 5.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W5 smd circle (at 6.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W4 smd circle (at 7.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad W3 smd circle (at 8.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad W2 smd circle (at 9.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 217 MKM_FPGA_CS_N))
-    (pad W1 smd circle (at 10.5 7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 219 MKM_FPGA_MOSI))
-    (pad V22 smd circle (at -10.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V21 smd circle (at -9.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad V20 smd circle (at -8.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 98 FMC_D28))
-    (pad V19 smd circle (at -7.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V18 smd circle (at -6.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 99 FMC_D29))
-    (pad V17 smd circle (at -5.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V16 smd circle (at -4.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad V15 smd circle (at -3.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V14 smd circle (at -2.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V13 smd circle (at -1.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V12 smd circle (at -0.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 160 FPGA_JTAG_TCK))
-    (pad V11 smd circle (at 0.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad V10 smd circle (at 1.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V9 smd circle (at 2.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V8 smd circle (at 3.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V7 smd circle (at 4.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad V6 smd circle (at 5.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad V5 smd circle (at 6.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 106 FMC_NE1))
-    (pad V4 smd circle (at 7.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 93 FMC_D23))
-    (pad V3 smd circle (at 8.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 220 MKM_FPGA_SCK))
-    (pad V2 smd circle (at 9.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 56 FMC_A13))
-    (pad V1 smd circle (at 10.5 6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad U22 smd circle (at -10.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 272 NetR65_1))
-    (pad U21 smd circle (at -9.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U20 smd circle (at -8.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 82 FMC_D12))
-    (pad U19 smd circle (at -7.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad U18 smd circle (at -6.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U17 smd circle (at -5.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U16 smd circle (at -4.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U15 smd circle (at -3.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U14 smd circle (at -2.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad U13 smd circle (at -1.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 162 FPGA_JTAG_TDO))
-    (pad U12 smd circle (at -0.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 153 FPGA_INIT_B_INT1))
-    (pad U11 smd circle (at 0.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 164 FPGA_M0))
-    (pad U10 smd circle (at 1.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 165 FPGA_M1))
-    (pad U9 smd circle (at 2.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 166 FPGA_M2))
-    (pad U8 smd circle (at 3.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad U7 smd circle (at 4.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U6 smd circle (at 5.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U5 smd circle (at 6.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad U4 smd circle (at 7.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad U3 smd circle (at 8.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 149 FPGA_GPIO_LED_0))
-    (pad U2 smd circle (at 9.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 73 FMC_D3))
-    (pad U1 smd circle (at 10.5 5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 72 FMC_D2))
-    (pad T22 smd circle (at -10.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad T21 smd circle (at -9.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T20 smd circle (at -8.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T19 smd circle (at -7.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 119 FPGA_CFG_CS_N1))
-    (pad T18 smd circle (at -6.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T17 smd circle (at -5.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad T16 smd circle (at -4.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T15 smd circle (at -3.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T14 smd circle (at -2.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T13 smd circle (at -1.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 163 FPGA_JTAG_TMS))
-    (pad T12 smd circle (at -0.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad T11 smd circle (at 0.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad T10 smd circle (at 1.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad T9 smd circle (at 2.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad T8 smd circle (at 3.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad T7 smd circle (at 4.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad T6 smd circle (at 5.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T5 smd circle (at 6.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T4 smd circle (at 7.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T3 smd circle (at 8.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad T2 smd circle (at 9.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad T1 smd circle (at 10.5 4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 150 FPGA_GPIO_LED_1))
-    (pad R22 smd circle (at -10.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 123 FPGA_CFG_MISO1))
-    (pad R21 smd circle (at -9.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 100 FMC_D30))
-    (pad R20 smd circle (at -8.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad R19 smd circle (at -7.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R18 smd circle (at -6.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R17 smd circle (at -5.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R16 smd circle (at -4.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R15 smd circle (at -3.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad R14 smd circle (at -2.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R13 smd circle (at -1.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 161 FPGA_JTAG_TDI))
-    (pad R12 smd circle (at -0.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad R11 smd circle (at 0.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad R10 smd circle (at 1.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad R9 smd circle (at 2.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad R8 smd circle (at 3.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad R7 smd circle (at 4.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad R6 smd circle (at 5.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R5 smd circle (at 6.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad R4 smd circle (at 7.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 95 FMC_D25))
-    (pad R3 smd circle (at 8.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R2 smd circle (at 9.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad R1 smd circle (at 10.5 3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P22 smd circle (at -10.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 125 FPGA_CFG_MOSI1))
-    (pad P21 smd circle (at -9.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 101 FMC_D31))
-    (pad P20 smd circle (at -8.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P19 smd circle (at -7.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P18 smd circle (at -6.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad P17 smd circle (at -5.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P16 smd circle (at -4.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P15 smd circle (at -3.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P14 smd circle (at -2.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P13 smd circle (at -1.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad P12 smd circle (at -0.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad P11 smd circle (at 0.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad P10 smd circle (at 1.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad P9 smd circle (at 2.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P9 smd circle (at 2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad P8 smd circle (at 3.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P8 smd circle (at 3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad P7 smd circle (at 4.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P7 smd circle (at 4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad P6 smd circle (at 5.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P5 smd circle (at 6.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P4 smd circle (at 7.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P3 smd circle (at 8.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P6 smd circle (at 5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P5 smd circle (at 6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P4 smd circle (at 7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P3 smd circle (at 8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad P2 smd circle (at 9.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad P1 smd circle (at 10.5 2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N22 smd circle (at -10.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N21 smd circle (at -9.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad P2 smd circle (at 9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad P1 smd circle (at 10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N22 smd circle (at -10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N21 smd circle (at -9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad N20 smd circle (at -8.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N19 smd circle (at -7.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N18 smd circle (at -6.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N17 smd circle (at -5.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N16 smd circle (at -4.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N20 smd circle (at -8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N19 smd circle (at -7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N18 smd circle (at -6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N17 smd circle (at -5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N16 smd circle (at -4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad N15 smd circle (at -3.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N15 smd circle (at -3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 81 FMC_D11))
-    (pad N14 smd circle (at -2.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N13 smd circle (at -1.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N12 smd circle (at -0.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N14 smd circle (at -2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N13 smd circle (at -1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N12 smd circle (at -0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 167 FPGA_PROGRAM_B1))
-    (pad N11 smd circle (at 0.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N11 smd circle (at 0.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad N10 smd circle (at 1.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N10 smd circle (at 1.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad N9 smd circle (at 2.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N9 smd circle (at 2.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad N8 smd circle (at 3.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N8 smd circle (at 3.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad N7 smd circle (at 4.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N7 smd circle (at 4.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad N6 smd circle (at 5.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N6 smd circle (at 5.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad N5 smd circle (at 6.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N4 smd circle (at 7.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N3 smd circle (at 8.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N2 smd circle (at 9.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad N1 smd circle (at 10.5 1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad N5 smd circle (at 6.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N4 smd circle (at 7.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N3 smd circle (at 8.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N2 smd circle (at 9.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad N1 smd circle (at 10.5 1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad M22 smd circle (at -10.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M21 smd circle (at -9.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M20 smd circle (at -8.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M19 smd circle (at -7.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad M18 smd circle (at -6.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M17 smd circle (at -5.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M16 smd circle (at -4.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M15 smd circle (at -3.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M14 smd circle (at -2.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M22 smd circle (at -10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M21 smd circle (at -9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M20 smd circle (at -8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M19 smd circle (at -7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad M18 smd circle (at -6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M17 smd circle (at -5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M16 smd circle (at -4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M15 smd circle (at -3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M14 smd circle (at -2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad M13 smd circle (at -1.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M12 smd circle (at -0.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M13 smd circle (at -1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M12 smd circle (at -0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad M11 smd circle (at 0.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M11 smd circle (at 0.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad M10 smd circle (at 1.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M10 smd circle (at 1.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad M9 smd circle (at 2.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M8 smd circle (at 3.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M9 smd circle (at 2.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M8 smd circle (at 3.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad M7 smd circle (at 4.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M7 smd circle (at 4.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad M6 smd circle (at 5.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M5 smd circle (at 6.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M4 smd circle (at 7.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M6 smd circle (at 5.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M5 smd circle (at 6.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M4 smd circle (at 7.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad M3 smd circle (at 8.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M2 smd circle (at 9.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad M1 smd circle (at 10.5 0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L22 smd circle (at -10.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad L21 smd circle (at -9.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L20 smd circle (at -8.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L19 smd circle (at -7.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L18 smd circle (at -6.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L17 smd circle (at -5.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad M3 smd circle (at 8.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M2 smd circle (at 9.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad M1 smd circle (at 10.5 0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L22 smd circle (at -10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad L21 smd circle (at -9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L20 smd circle (at -8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L19 smd circle (at -7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L18 smd circle (at -6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L17 smd circle (at -5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad L16 smd circle (at -4.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L15 smd circle (at -3.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L14 smd circle (at -2.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L13 smd circle (at -1.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L12 smd circle (at -0.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad L16 smd circle (at -4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L15 smd circle (at -3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L14 smd circle (at -2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L13 smd circle (at -1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L12 smd circle (at -0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 127 FPGA_CFG_SCLK1))
-    (pad L11 smd circle (at 0.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad L11 smd circle (at 0.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad L10 smd circle (at 1.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L9 smd circle (at 2.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad L10 smd circle (at 1.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L9 smd circle (at 2.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad L8 smd circle (at 3.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad L8 smd circle (at 3.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad L7 smd circle (at 4.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad L7 smd circle (at 4.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad L6 smd circle (at 5.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L5 smd circle (at 6.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L4 smd circle (at 7.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L3 smd circle (at 8.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad L2 smd circle (at 9.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad L1 smd circle (at 10.5 -0.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K22 smd circle (at -10.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K21 smd circle (at -9.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K20 smd circle (at -8.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad L6 smd circle (at 5.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L5 smd circle (at 6.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L4 smd circle (at 7.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L3 smd circle (at 8.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad L2 smd circle (at 9.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad L1 smd circle (at 10.5 -0.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K22 smd circle (at -10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K21 smd circle (at -9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K20 smd circle (at -8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad K19 smd circle (at -7.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K18 smd circle (at -6.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K17 smd circle (at -5.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K16 smd circle (at -4.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K15 smd circle (at -3.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad K14 smd circle (at -2.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K13 smd circle (at -1.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K12 smd circle (at -0.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad K19 smd circle (at -7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K18 smd circle (at -6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K17 smd circle (at -5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K16 smd circle (at -4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K15 smd circle (at -3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad K14 smd circle (at -2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K13 smd circle (at -1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K12 smd circle (at -0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad K11 smd circle (at 0.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad K11 smd circle (at 0.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad K10 smd circle (at 1.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad K10 smd circle (at 1.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad K9 smd circle (at 2.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad K9 smd circle (at 2.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad K8 smd circle (at 3.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad K8 smd circle (at 3.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad K7 smd circle (at 4.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad K6 smd circle (at 5.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K5 smd circle (at 6.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad K4 smd circle (at 7.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K3 smd circle (at 8.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K2 smd circle (at 9.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad K1 smd circle (at 10.5 -1.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J22 smd circle (at -10.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J21 smd circle (at -9.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J20 smd circle (at -8.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J19 smd circle (at -7.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J18 smd circle (at -6.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad J17 smd circle (at -5.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J16 smd circle (at -4.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J15 smd circle (at -3.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J14 smd circle (at -2.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J13 smd circle (at -1.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad K7 smd circle (at 4.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad K6 smd circle (at 5.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K5 smd circle (at 6.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad K4 smd circle (at 7.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K3 smd circle (at 8.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K2 smd circle (at 9.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad K1 smd circle (at 10.5 -1.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J22 smd circle (at -10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J21 smd circle (at -9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J20 smd circle (at -8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J19 smd circle (at -7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J18 smd circle (at -6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad J17 smd circle (at -5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J16 smd circle (at -4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J15 smd circle (at -3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J14 smd circle (at -2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J13 smd circle (at -1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad J12 smd circle (at -0.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J12 smd circle (at -0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad J11 smd circle (at 0.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J11 smd circle (at 0.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad J10 smd circle (at 1.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J10 smd circle (at 1.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad J9 smd circle (at 2.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J9 smd circle (at 2.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad J8 smd circle (at 3.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J8 smd circle (at 3.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad J7 smd circle (at 4.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J7 smd circle (at 4.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad J6 smd circle (at 5.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J5 smd circle (at 6.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J4 smd circle (at 7.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J3 smd circle (at 8.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J6 smd circle (at 5.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J5 smd circle (at 6.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J4 smd circle (at 7.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J3 smd circle (at 8.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad J2 smd circle (at 9.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad J1 smd circle (at 10.5 -2.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H22 smd circle (at -10.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H21 smd circle (at -9.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad H20 smd circle (at -8.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H19 smd circle (at -7.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H18 smd circle (at -6.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H17 smd circle (at -5.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H16 smd circle (at -4.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad J2 smd circle (at 9.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad J1 smd circle (at 10.5 -2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H22 smd circle (at -10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H21 smd circle (at -9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad H20 smd circle (at -8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H19 smd circle (at -7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H18 smd circle (at -6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H17 smd circle (at -5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H16 smd circle (at -4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad H15 smd circle (at -3.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H14 smd circle (at -2.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H13 smd circle (at -1.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H12 smd circle (at -0.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H15 smd circle (at -3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H14 smd circle (at -2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H13 smd circle (at -1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H12 smd circle (at -0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 174 FPGA_VCCAUX_1V8))
-    (pad H11 smd circle (at 0.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H11 smd circle (at 0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad H10 smd circle (at 1.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H10 smd circle (at 1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad H9 smd circle (at 2.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H9 smd circle (at 2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad H8 smd circle (at 3.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H8 smd circle (at 3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 175 FPGA_VCCINT_1V0))
-    (pad H7 smd circle (at 4.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H7 smd circle (at 4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad H6 smd circle (at 5.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H6 smd circle (at 5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad H5 smd circle (at 6.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H4 smd circle (at 7.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H3 smd circle (at 8.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H2 smd circle (at 9.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad H1 smd circle (at 10.5 -3.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad G22 smd circle (at -10.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G21 smd circle (at -9.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G20 smd circle (at -8.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G19 smd circle (at -7.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad H5 smd circle (at 6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H4 smd circle (at 7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H3 smd circle (at 8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H2 smd circle (at 9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad H1 smd circle (at 10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad G22 smd circle (at -10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G21 smd circle (at -9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G20 smd circle (at -8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G19 smd circle (at -7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad G18 smd circle (at -6.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G17 smd circle (at -5.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G16 smd circle (at -4.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G15 smd circle (at -3.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G14 smd circle (at -2.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G18 smd circle (at -6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G17 smd circle (at -5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G16 smd circle (at -4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G15 smd circle (at -3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G14 smd circle (at -2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G13 smd circle (at -1.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G12 smd circle (at -0.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G13 smd circle (at -1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G12 smd circle (at -0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G11 smd circle (at 0.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G11 smd circle (at 0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 129 FPGA_DONE_INT))
-    (pad G10 smd circle (at 1.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G10 smd circle (at 1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G9 smd circle (at 2.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G9 smd circle (at 2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G8 smd circle (at 3.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G8 smd circle (at 3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G7 smd circle (at 4.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G7 smd circle (at 4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G6 smd circle (at 5.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G6 smd circle (at 5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G5 smd circle (at 6.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G5 smd circle (at 6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad G4 smd circle (at 7.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G3 smd circle (at 8.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G2 smd circle (at 9.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad G1 smd circle (at 10.5 -4.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F22 smd circle (at -10.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad G4 smd circle (at 7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G3 smd circle (at 8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G2 smd circle (at 9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad G1 smd circle (at 10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F22 smd circle (at -10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad F21 smd circle (at -9.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F20 smd circle (at -8.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F19 smd circle (at -7.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F18 smd circle (at -6.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F17 smd circle (at -5.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad F21 smd circle (at -9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F20 smd circle (at -8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F19 smd circle (at -7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F18 smd circle (at -6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F17 smd circle (at -5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad F16 smd circle (at -4.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad F16 smd circle (at -4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 157 FPGA_IRQ_N_1))
-    (pad F15 smd circle (at -3.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F14 smd circle (at -2.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad F15 smd circle (at -3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F14 smd circle (at -2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 156 FPGA_IRQ_N_0))
-    (pad F13 smd circle (at -1.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F12 smd circle (at -0.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad F13 smd circle (at -1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F12 smd circle (at -0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad F11 smd circle (at 0.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad F10 smd circle (at 1.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F9 smd circle (at 2.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F8 smd circle (at 3.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F7 smd circle (at 4.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F6 smd circle (at 5.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F5 smd circle (at 6.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad F4 smd circle (at 7.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F3 smd circle (at 8.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad F2 smd circle (at 9.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad F11 smd circle (at 0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad F10 smd circle (at 1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F9 smd circle (at 2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F8 smd circle (at 3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F7 smd circle (at 4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F6 smd circle (at 5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F5 smd circle (at 6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad F4 smd circle (at 7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F3 smd circle (at 8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad F2 smd circle (at 9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad F1 smd circle (at 10.5 -5.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E22 smd circle (at -10.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E21 smd circle (at -9.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E20 smd circle (at -8.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad E19 smd circle (at -7.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E18 smd circle (at -6.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E17 smd circle (at -5.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad F1 smd circle (at 10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E22 smd circle (at -10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E21 smd circle (at -9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E20 smd circle (at -8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad E19 smd circle (at -7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E18 smd circle (at -6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E17 smd circle (at -5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 158 FPGA_IRQ_N_2))
-    (pad E16 smd circle (at -4.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E15 smd circle (at -3.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E16 smd circle (at -4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E15 smd circle (at -3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad E14 smd circle (at -2.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E14 smd circle (at -2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 133 FPGA_GPIO_A_0))
-    (pad E13 smd circle (at -1.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E13 smd circle (at -1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 134 FPGA_GPIO_A_1))
-    (pad E12 smd circle (at -0.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E12 smd circle (at -0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad E11 smd circle (at 0.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E11 smd circle (at 0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad E10 smd circle (at 1.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E9 smd circle (at 2.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E10 smd circle (at 1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E9 smd circle (at 2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad E8 smd circle (at 3.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E7 smd circle (at 4.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E8 smd circle (at 3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E7 smd circle (at 4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad E6 smd circle (at 5.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E5 smd circle (at 6.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E6 smd circle (at 5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E5 smd circle (at 6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad E4 smd circle (at 7.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E4 smd circle (at 7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad E3 smd circle (at 8.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E2 smd circle (at 9.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad E1 smd circle (at 10.5 -6.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D22 smd circle (at -10.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D21 smd circle (at -9.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D20 smd circle (at -8.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D19 smd circle (at -7.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D18 smd circle (at -6.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad E3 smd circle (at 8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E2 smd circle (at 9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad E1 smd circle (at 10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D22 smd circle (at -10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D21 smd circle (at -9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D20 smd circle (at -8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D19 smd circle (at -7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D18 smd circle (at -6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad D17 smd circle (at -5.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D17 smd circle (at -5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 132 FPGA_GCLK))
-    (pad D16 smd circle (at -4.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D15 smd circle (at -3.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D14 smd circle (at -2.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D16 smd circle (at -4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D15 smd circle (at -3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D14 smd circle (at -2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 144 FPGA_GPIO_B_3))
-    (pad D13 smd circle (at -1.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D13 smd circle (at -1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad D12 smd circle (at -0.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D12 smd circle (at -0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad D11 smd circle (at 0.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D10 smd circle (at 1.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D9 smd circle (at 2.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D8 smd circle (at 3.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D11 smd circle (at 0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D10 smd circle (at 1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D9 smd circle (at 2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad D7 smd circle (at 4.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D6 smd circle (at 5.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D5 smd circle (at 6.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D4 smd circle (at 7.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad D3 smd circle (at 8.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad D2 smd circle (at 9.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad D1 smd circle (at 10.5 -7.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C22 smd circle (at -10.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 148 FPGA_GPIO_B_7))
-    (pad C21 smd circle (at -9.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad C20 smd circle (at -8.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C20 smd circle (at -8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 147 FPGA_GPIO_B_6))
-    (pad C19 smd circle (at -7.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C18 smd circle (at -6.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C19 smd circle (at -7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C18 smd circle (at -6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 145 FPGA_GPIO_B_4))
-    (pad C17 smd circle (at -5.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C16 smd circle (at -4.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C17 smd circle (at -5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C16 smd circle (at -4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad C15 smd circle (at -3.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C15 smd circle (at -3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 142 FPGA_GPIO_B_1))
-    (pad C14 smd circle (at -2.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C14 smd circle (at -2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 159 FPGA_IRQ_N_3))
-    (pad C13 smd circle (at -1.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C13 smd circle (at -1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 137 FPGA_GPIO_A_4))
-    (pad C12 smd circle (at -0.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C12 smd circle (at -0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad C11 smd circle (at 0.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C10 smd circle (at 1.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C11 smd circle (at 0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad C9 smd circle (at 2.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C8 smd circle (at 3.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C7 smd circle (at 4.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C6 smd circle (at 5.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad C5 smd circle (at 6.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C4 smd circle (at 7.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C3 smd circle (at 8.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad C2 smd circle (at 9.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad C1 smd circle (at 10.5 -8.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad C2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad C1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad B22 smd circle (at -10.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B21 smd circle (at -9.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B20 smd circle (at -8.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 29 AVR_GPIO_FPGA_0))
-    (pad B19 smd circle (at -7.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad B18 smd circle (at -6.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 131 FPGA_ENTROPY_DISABLE))
-    (pad B17 smd circle (at -5.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B16 smd circle (at -4.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 143 FPGA_GPIO_B_2))
-    (pad B15 smd circle (at -3.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 140 FPGA_GPIO_A_7))
-    (pad B14 smd circle (at -2.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad B13 smd circle (at -1.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 138 FPGA_GPIO_A_5))
-    (pad B12 smd circle (at -0.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad B11 smd circle (at 0.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B10 smd circle (at 1.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B9 smd circle (at 2.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B8 smd circle (at 3.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B7 smd circle (at 4.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B6 smd circle (at 5.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B5 smd circle (at 6.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B4 smd circle (at 7.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B3 smd circle (at 8.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad B2 smd circle (at 9.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad B1 smd circle (at 10.5 -9.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad A22 smd circle (at -10.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
-      (net 6 GND))
-    (pad A21 smd circle (at -9.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
+      (net 6 GND))
+    (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 146 FPGA_GPIO_B_5))
-    (pad A20 smd circle (at -8.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 30 AVR_GPIO_FPGA_1))
-    (pad A19 smd circle (at -7.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 32 AVR_GPIO_FPGA_3))
-    (pad A18 smd circle (at -6.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 31 AVR_GPIO_FPGA_2))
-    (pad A17 smd circle (at -5.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 302 VCCO_3V3))
-    (pad A16 smd circle (at -4.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 141 FPGA_GPIO_B_0))
-    (pad A15 smd circle (at -3.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 139 FPGA_GPIO_A_6))
-    (pad A14 smd circle (at -2.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 136 FPGA_GPIO_A_3))
-    (pad A13 smd circle (at -1.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 135 FPGA_GPIO_A_2))
-    (pad A12 smd circle (at -0.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A11 smd circle (at 0.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A10 smd circle (at 1.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad A9 smd circle (at 2.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A8 smd circle (at 3.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad A7 smd circle (at 4.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A6 smd circle (at 5.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad A5 smd circle (at 6.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A4 smd circle (at 7.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
-    (pad A3 smd circle (at 8.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
+    (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A2 smd circle (at 9.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask)
+    (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)
       (net 6 GND))
-    (pad A1 smd circle (at 10.5 -10.5 180) (size 0.449999 0.449999) (layers B.Cu B.Paste B.Mask))
+    (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/041B98A5-F02D.wrl
       (at (xyz 0 0 0))
       (scale (xyz 1 1 1))
@@ -10922,9 +10922,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0 0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
-    (pad 2 smd rect (at 0 -0.5 90) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 166 FPGA_M2))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -10943,9 +10943,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 2 smd rect (at 0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 165 FPGA_M1))
-    (pad 1 smd rect (at -0.5 0) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 6 GND))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -10964,9 +10964,9 @@
     (fp_text value "" (at 0 0) (layer F.SilkS) hide
       (effects (font (thickness 0.05)))
     )
-    (pad 1 smd rect (at 0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 164 FPGA_M0))
-    (pad 2 smd rect (at -0.5 0 180) (size 0.449999 0.599999) (layers F.Cu F.Paste F.Mask)
+    (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask)
       (net 302 VCCO_3V3))
     (model /home/ft/work/cryptech/official/user/ft/alpha_to_kicad/rev03-Altium/wrlshp/537E0B02-A9B3.wrl
       (at (xyz 0 0 0))
@@ -17165,7 +17165,7 @@
   (gr_line (start 72.32 -100.2454) (end 95.32 -100.2454) (layer B.CrtYd) (width 0.254))
   (gr_line (start 95.32 -77.7454) (end 95.32 -100.2454) (layer B.CrtYd) (width 0.254))
   (gr_text "USB-\r\nUART" (at 57.25 -10.525 90) (layer F.SilkS)
-    (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+    (effects (font (size 1 1) (thickness 0.1)) (justify left))
   )
   (gr_text "Alpha rev.03\r\nRadically Open BSD License\r\nhttps://cryptech.is/" (at 16.4 -55.7 90) (layer F.SilkS)
     (effects (font (size 1.599999 1.599999) (thickness 0.1)) (justify left))
@@ -17174,754 +17174,754 @@
     (effects (font (size 1.5 1.5) (thickness 0.1)) (justify left))
   )
   (gr_text JP5 (at 30.8 4.2) (layer F.SilkS)
-    (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+    (effects (font (size 1 1) (thickness 0.1)) (justify left))
   )
   (gr_text JP6 (at 82.85 -27.25) (layer F.SilkS)
-    (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+    (effects (font (size 1 1) (thickness 0.1)) (justify left))
   )
   (gr_text C7 (at 72.35 -84.275) (layer F.SilkS)
-    (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+    (effects (font (size 1 1) (thickness 0.1)) (justify left))
   )
   (gr_text C11 (at 76.15 -89.9 90) (layer F.SilkS)
-    (effects (font (size 1.000001 1.000001) (thickness 0.1)) (justify left))
+    (effects (font (size 1 1) (thickness 0.1)) (justify left))
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@@ -19451,40 +19451,40 @@
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+  (segment (start 73.875 -74.575) (end 74.3 -74.15) (width 1) (layer F.Cu) (net 6))
+  (segment (start 74.3 -73.3) (end 74.3 -74.15) (width 1) (layer F.Cu) (net 6))
   (segment (start 94.0562 -61.4934) (end 94.1 -61.5372) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 94.1 -61.5372) (end 94.1 -62) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 92.1004 -57.8264) (end 93.2736 -57.8264) (width 0.299999) (layer F.Cu) (net 6))
@@ -21497,7 +21497,7 @@
   (segment (start 37.8 -21) (end 37.8 -21.6) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 39.2 -20.8) (end 39.2 -21.4) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 40.4702 -20.0406) (end 40.4702 -20.7298) (width 0.299999) (layer F.Cu) (net 6))
-  (segment (start 69.2 -53) (end 69.6 -52.6) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 69.2 -53) (end 69.6 -52.6) (width 1) (layer F.Cu) (net 6))
   (segment (start 80.2268 -53.3264) (end 81.4014 -53.3264) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 81.4014 -53.3264) (end 81.45 -53.375) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 43.9234 -62.8984) (end 44.6786 -62.8984) (width 0.299999) (layer F.Cu) (net 6))
@@ -21507,12 +21507,12 @@
   (segment (start 80.2032 -56.35) (end 80.2268 -56.3264) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 78.4306 -56.35) (end 80.2032 -56.35) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 78.105 -56.0244) (end 78.4306 -56.35) (width 0.299999) (layer F.Cu) (net 6))
-  (segment (start 67.975 -51.65) (end 67.975 -53.05) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 67.1875 -52.2625) (end 67.42246 -52.02754) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 67.1875 -52.2625) (end 67.975 -53.05) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 65.05317 -52.70257) (end 65.05317 -53.00318) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 65.05317 -53.00318) (end 65.475 -53.425) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 65.475 -53.425) (end 65.475 -54.118) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 67.975 -51.65) (end 67.975 -53.05) (width 1) (layer F.Cu) (net 6))
+  (segment (start 67.1875 -52.2625) (end 67.42246 -52.02754) (width 1) (layer F.Cu) (net 6))
+  (segment (start 67.1875 -52.2625) (end 67.975 -53.05) (width 1) (layer F.Cu) (net 6))
+  (segment (start 65.05317 -52.70257) (end 65.05317 -53.00318) (width 1) (layer F.Cu) (net 6))
+  (segment (start 65.05317 -53.00318) (end 65.475 -53.425) (width 1) (layer F.Cu) (net 6))
+  (segment (start 65.475 -53.425) (end 65.475 -54.118) (width 1) (layer F.Cu) (net 6))
   (segment (start 78.8108 -39.3108) (end 80.2268 -39.3108) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 79.32559 -46.3212) (end 80.2268 -46.3212) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 79.13167 -46.12728) (end 79.32559 -46.3212) (width 0.299999) (layer F.Cu) (net 6))
@@ -21530,8 +21530,8 @@
   (segment (start 90.6526 -20.1102) (end 91.9052 -20.1102) (width 0.2) (layer F.Cu) (net 6))
   (segment (start 91.9052 -20.1102) (end 92.202 -19.8134) (width 0.2) (layer F.Cu) (net 6))
   (segment (start 92.202 -19.8134) (end 93.1634 -19.8134) (width 0.2) (layer F.Cu) (net 6))
-  (segment (start 88.032 -24.968) (end 88.9338 -24.968) (width 0.599999) (layer F.Cu) (net 6))
-  (segment (start 89.032 -24.032) (end 89.032 -24.9338) (width 0.599999) (layer F.Cu) (net 6))
+  (segment (start 88.032 -24.968) (end 88.9338 -24.968) (width 0.6) (layer F.Cu) (net 6))
+  (segment (start 89.032 -24.032) (end 89.032 -24.9338) (width 0.6) (layer F.Cu) (net 6))
   (segment (start 83.6354 -22.1168) (end 83.6354 -23.0396) (width 0.2) (layer F.Cu) (net 6))
   (segment (start 79.6554 -18.6196) (end 80.391 -18.6196) (width 0.2) (layer F.Cu) (net 6))
   (segment (start 80.391 -18.6196) (end 82.1274 -18.6196) (width 0.15) (layer F.Cu) (net 6))
@@ -21580,9 +21580,9 @@
   (segment (start 70.25 -98.25) (end 71.25 -98.25) (width 0.15) (layer F.Cu) (net 6))
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   (segment (start 71.5 -85.25) (end 71.5 -86.5) (width 0.299999) (layer F.Cu) (net 6))
-  (segment (start 76.25 -85) (end 76.25 -86.75) (width 0.499999) (layer F.Cu) (net 6))
-  (segment (start 75.25 -84) (end 76.25 -85) (width 0.499999) (layer F.Cu) (net 6))
-  (segment (start 71.5 -84) (end 75.25 -84) (width 0.499999) (layer F.Cu) (net 6))
+  (segment (start 76.25 -85) (end 76.25 -86.75) (width 0.5) (layer F.Cu) (net 6))
+  (segment (start 75.25 -84) (end 76.25 -85) (width 0.5) (layer F.Cu) (net 6))
+  (segment (start 71.5 -84) (end 75.25 -84) (width 0.5) (layer F.Cu) (net 6))
   (segment (start 27.5 -78.1) (end 27.5 -78.7) (width 0.299999) (layer F.Cu) (net 6))
   (segment (start 30.673 -76.827) (end 30.9118 -76.827) (width 0.15) (layer F.Cu) (net 6))
   (segment (start 30.2 -77.3) (end 30.673 -76.827) (width 0.15) (layer F.Cu) (net 6))
@@ -21618,14 +21618,14 @@
   (segment (start 52.5 -43.95) (end 52.5 -44.3821) (width 0.2) (layer F.Cu) (net 6))
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   (segment (start 90.4064 -74.0004) (end 91.325 -74.0004) (width 0.2) (layer F.Cu) (net 6))
-  (segment (start 48.45 -55) (end 48.45 -56.0832) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 48.45 -55) (end 48.45 -56.0832) (width 1) (layer F.Cu) (net 6))
   (segment (start 44.6024 -75.8618) (end 44.6024 -76.3524) (width 0.2) (layer F.Cu) (net 6))
-  (segment (start 42.875 -70.675) (end 43.9288 -70.675) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 42.875 -70.675) (end 43.9288 -70.675) (width 1) (layer F.Cu) (net 6))
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   (segment (start 35.925 -59.1) (end 36.5153 -59.1) (width 0.2) (layer F.Cu) (net 6))
-  (segment (start 40.6 -66.125) (end 41.2 -66.125) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 42.075 -54.475) (end 42.1 -54.45) (width 1.000001) (layer F.Cu) (net 6))
-  (segment (start 42.1 -52.675) (end 42.1 -54.45) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 40.6 -66.125) (end 41.2 -66.125) (width 1) (layer F.Cu) (net 6))
+  (segment (start 42.075 -54.475) (end 42.1 -54.45) (width 1) (layer F.Cu) (net 6))
+  (segment (start 42.1 -52.675) (end 42.1 -54.45) (width 1) (layer F.Cu) (net 6))
   (segment (start 33.1482 -29.6482) (end 34.3522 -29.6482) (width 0.15) (layer F.Cu) (net 6))
   (segment (start 32.6 -29.1) (end 33.1482 -29.6482) (width 0.15) (layer F.Cu) (net 6))
   (segment (start 42.4634 -23.3782) (end 43.7032 -23.3782) (width 0.15) (layer F.Cu) (net 6))
@@ -21649,10 +21649,10 @@
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   (segment (start 42.375 -44.8) (end 43.1076 -44.0674) (width 0.299999) (layer F.Cu) (net 6))
-  (segment (start 69.70001 -53.025) (end 70.8 -53.025) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 69.70001 -53.025) (end 70.8 -53.025) (width 1) (layer F.Cu) (net 6))
   (segment (start 18.055 -11.375) (end 18.0686 -11.3886) (width 0.15) (layer F.Cu) (net 6))
   (segment (start 16.5792 -11.375) (end 18.055 -11.375) (width 0.15) (layer F.Cu) (net 6))
-  (segment (start 66.47824 -52.02754) (end 67.42246 -52.02754) (width 1.000001) (layer F.Cu) (net 6))
+  (segment (start 66.47824 -52.02754) (end 67.42246 -52.02754) (width 1) (layer F.Cu) (net 6))
   (segment (start 81.2368 -9.6382) (end 81.4328 -9.6382) (width 0.2) (layer F.Cu) (net 6))
   (segment (start 80.35 -10.525) (end 81.2368 -9.6382) (width 0.2) (layer F.Cu) (net 6))
   (segment (start 83.6426 -7.9364) (end 83.82862 -7.75038) (width 0.2) (layer F.Cu) (net 6))
@@ -21692,9 +21692,9 @@
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   (segment (start 82.1436 -85.1408) (end 83.1088 -86.106) (width 0.299999) (layer B.Cu) (net 8))
-  (via (at 48.5 -34.425) (size 0.499999) (layers F.Cu B.Cu) (net 9))
-  (via (at 55.55 -40.375) (size 0.499999) (layers F.Cu B.Cu) (net 9))
-  (via (at 45.925 -33.475) (size 0.499999) (layers F.Cu B.Cu) (net 9))
+  (via micro (at 48.5 -34.425) (size 0.5) (layers F.Cu B.Cu) (net 9))
+  (via micro (at 55.55 -40.375) (size 0.5) (layers F.Cu B.Cu) (net 9))
+  (via micro (at 45.925 -33.475) (size 0.5) (layers F.Cu B.Cu) (net 9))
   (segment (start 58.375 -42.725) (end 61.4426 -45.7926) (width 0.164) (layer B.Cu) (net 9))
   (segment (start 57.9 -42.725) (end 58.375 -42.725) (width 0.164) (layer B.Cu) (net 9))
   (segment (start 55.55 -40.375) (end 57.9 -42.725) (width 0.164) (layer B.Cu) (net 9))
@@ -21713,10 +21713,10 @@
   (segment (start 55.55 -37.95) (end 55.55 -40.375) (width 0.164) (layer F.Cu) (net 9))
   (segment (start 47.55 -33.475) (end 48.5 -34.425) (width 0.164) (layer In2.Cu) (net 9))
   (segment (start 45.925 -33.475) (end 47.55 -33.475) (width 0.164) (layer In2.Cu) (net 9))
-  (via (at 37.982 -42.62126) (size 0.499999) (layers F.Cu B.Cu) (net 10))
-  (via (at 66.31364 -44.843) (size 0.499999) (layers F.Cu B.Cu) (net 10))
-  (via (at 46 -41.875) (size 0.499999) (layers F.Cu B.Cu) (net 10))
-  (via (at 67.25 -41.6) (size 0.499999) (layers F.Cu B.Cu) (net 10))
+  (via micro (at 37.982 -42.62126) (size 0.5) (layers F.Cu B.Cu) (net 10))
+  (via micro (at 66.31364 -44.843) (size 0.5) (layers F.Cu B.Cu) (net 10))
+  (via micro (at 46 -41.875) (size 0.5) (layers F.Cu B.Cu) (net 10))
+  (via micro (at 67.25 -41.6) (size 0.5) (layers F.Cu B.Cu) (net 10))
   (segment (start 63.2714 -44.8564) (end 63.2848 -44.843) (width 0.15) (layer B.Cu) (net 10))
   (segment (start 37.982 -42.62126) (end 38.25374 -42.62126) (width 0.15) (layer B.Cu) (net 10))
   (segment (start 38.25374 -42.62126) (end 39.475 -41.4) (width 0.15) (layer B.Cu) (net 10))
@@ -21738,9 +21738,9 @@
   (segment (start 46 -41.475) (end 48.025 -39.45) (width 0.15) (layer In5.Cu) (net 10))
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   (segment (start 62.1 -39.45) (end 63.2396 -40.5896) (width 0.15) (layer In5.Cu) (net 10))
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-  (via (at 64.8 -44.35) (size 0.499999) (layers F.Cu B.Cu) (net 11))
-  (via (at 61.975 -35.6) (size 0.499999) (layers F.Cu B.Cu) (net 11))
+  (via micro (at 48.00234 -31.12652) (size 0.5) (layers F.Cu B.Cu) (net 11))
+  (via micro (at 64.8 -44.35) (size 0.5) (layers F.Cu B.Cu) (net 11))
+  (via micro (at 61.975 -35.6) (size 0.5) (layers F.Cu B.Cu) (net 11))
   (segment (start 63.2714 -44.3738) (end 64.6738 -44.3738) (width 0.15) (layer B.Cu) (net 11))
   (segment (start 64.8 -44.5) (end 64.85 -44.5) (width 0.15) (layer B.Cu) (net 11))
   (segment (start 64.6738 -44.3738) (end 64.8 -44.5) (width 0.15) (layer B.Cu) (net 11))
@@ -21764,9 +21764,9 @@
   (segment (start 61.475 -35.1) (end 61.975 -35.6) (width 0.15) (layer In5.Cu) (net 11))
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-  (via (at 42.025 -37.425) (size 0.499999) (layers F.Cu B.Cu) (net 12))
-  (via (at 61.85 -37.25) (size 0.499999) (layers F.Cu B.Cu) (net 12))
+  (via micro (at 61.725 -44.875) (size 0.5) (layers F.Cu B.Cu) (net 12))
+  (via micro (at 42.025 -37.425) (size 0.5) (layers F.Cu B.Cu) (net 12))
+  (via micro (at 61.85 -37.25) (size 0.5) (layers F.Cu B.Cu) (net 12))
   (segment (start 62.2144 -45.3644) (end 63.2714 -45.3644) (width 0.15) (layer B.Cu) (net 12))
   (segment (start 61.725 -44.875) (end 62.2144 -45.3644) (width 0.15) (layer B.Cu) (net 12))
   (segment (start 43.0026 -36.4474) (end 44.3852 -36.4474) (width 0.164) (layer F.Cu) (net 12))
@@ -21779,8 +21779,8 @@
   (segment (start 43.9 -37.425) (end 44.675 -38.2) (width 0.15) (layer In5.Cu) (net 12))
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   (segment (start 60.9 -38.2) (end 61.85 -37.25) (width 0.15) (layer In5.Cu) (net 12))
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-  (via (at 41.9 -8.075) (size 0.499999) (layers F.Cu B.Cu) (net 13))
+  (via micro (at 45.975 -14.125) (size 0.5) (layers F.Cu B.Cu) (net 13))
+  (via micro (at 41.9 -8.075) (size 0.5) (layers F.Cu B.Cu) (net 13))
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   (segment (start 45.975 -14.125) (end 45.975 -14.65) (width 0.15) (layer B.Cu) (net 13))
@@ -21789,8 +21789,8 @@
   (segment (start 45.975 -12.175) (end 45.975 -14.125) (width 0.15) (layer F.Cu) (net 13))
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-  (via (at 46.925 -8.7) (size 0.499999) (layers F.Cu B.Cu) (net 14))
+  (via micro (at 47.35231 -9.72547) (size 0.5) (layers F.Cu B.Cu) (net 14))
+  (via micro (at 46.925 -8.7) (size 0.5) (layers F.Cu B.Cu) (net 14))
   (segment (start 45.9486 -15.3736) (end 45.9486 -18.034) (width 0.15) (layer B.Cu) (net 14))
   (segment (start 45.5 -14.925) (end 45.9486 -15.3736) (width 0.15) (layer B.Cu) (net 14))
   (segment (start 45.5 -11.6) (end 45.5 -14.925) (width 0.15) (layer B.Cu) (net 14))
@@ -21801,8 +21801,8 @@
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-  (via (at 44.72718 -8.72543) (size 0.499999) (layers F.Cu B.Cu) (net 15))
+  (via micro (at 45.8 -10.1) (size 0.5) (layers F.Cu B.Cu) (net 15))
+  (via micro (at 44.72718 -8.72543) (size 0.5) (layers F.Cu B.Cu) (net 15))
   (segment (start 45.4406 -15.6906) (end 45.4406 -18.034) (width 0.15) (layer B.Cu) (net 15))
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   (segment (start 45.025 -11) (end 45.025 -15.275) (width 0.15) (layer B.Cu) (net 15))
@@ -21816,8 +21816,8 @@
   (segment (start 44.7 -9) (end 45.8 -10.1) (width 0.15) (layer F.Cu) (net 15))
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-  (via (at 43.45 -8.75) (size 0.499999) (layers F.Cu B.Cu) (net 16))
-  (via (at 44.625 -9.925) (size 0.499999) (layers F.Cu B.Cu) (net 16))
+  (via micro (at 43.45 -8.75) (size 0.5) (layers F.Cu B.Cu) (net 16))
+  (via micro (at 44.625 -9.925) (size 0.5) (layers F.Cu B.Cu) (net 16))
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   (segment (start 44.625 -9.875) (end 44.625 -16.075) (width 0.15) (layer B.Cu) (net 16))
@@ -21825,7 +21825,7 @@
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-  (via (at 53.925 -36.6) (size 0.499999) (layers F.Cu B.Cu) (net 17))
+  (via micro (at 53.925 -36.6) (size 0.5) (layers F.Cu B.Cu) (net 17))
   (segment (start 53.8684 -36.5434) (end 53.925 -36.6) (width 0.164) (layer F.Cu) (net 17))
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   (segment (start 92.47369 3) (end 96.5 -1.02631) (width 0.15) (layer In5.Cu) (net 17))
@@ -21847,7 +21847,7 @@
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-  (via (at 54.125 -35.95) (size 0.499999) (layers F.Cu B.Cu) (net 18))
+  (via micro (at 54.125 -35.95) (size 0.5) (layers F.Cu B.Cu) (net 18))
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@@ -29006,15 +29006,15 @@
   (segment (start 37.9556 -19.4444) (end 37.9556 -20.0406) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 37.9556 -19.4444) (end 38 -19.4) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 38.7 -19.3) (end 39.2 -19.8) (width 0.299999) (layer F.Cu) (net 302))
-  (segment (start 46.425 -54.55) (end 46.425 -56.0832) (width 1.000001) (layer F.Cu) (net 302))
-  (segment (start 62.87098 -55.74298) (end 63.246 -55.74298) (width 0.599999) (layer F.Cu) (net 302))
+  (segment (start 46.425 -54.55) (end 46.425 -56.0832) (width 1) (layer F.Cu) (net 302))
+  (segment (start 62.87098 -55.74298) (end 63.246 -55.74298) (width 0.6) (layer F.Cu) (net 302))
   (segment (start 78.09279 -44.85219) (end 78.105 -44.8644) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 77.45378 -44.85219) (end 78.09279 -44.85219) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 78.105 -55.0244) (end 78.20176 -54.92764) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 78.20176 -54.92764) (end 78.45589 -54.92764) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 78.45589 -54.92764) (end 78.55713 -54.8264) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 78.55713 -54.8264) (end 80.2268 -54.8264) (width 0.299999) (layer F.Cu) (net 302))
-  (segment (start 65.4558 -56.1) (end 66.6 -56.1) (width 1.000001) (layer F.Cu) (net 302))
+  (segment (start 65.4558 -56.1) (end 66.6 -56.1) (width 1) (layer F.Cu) (net 302))
   (segment (start 91.2918 -13.6332) (end 92.1084 -13.6332) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 12.85 -32.275) (end 12.9 -32.325) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 12.85 -31.75) (end 12.85 -32.275) (width 0.299999) (layer F.Cu) (net 302))
@@ -29050,8 +29050,8 @@
   (segment (start 83.70408 -71.05347) (end 83.70408 -71.72469) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 44.55217 -60.70217) (end 44.7 -60.85) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 44.55217 -60.37795) (end 44.55217 -60.70217) (width 0.299999) (layer F.Cu) (net 302))
-  (segment (start 39 -64.825) (end 39.7822 -64.0428) (width 1.000001) (layer F.Cu) (net 302))
-  (segment (start 39.7822 -64.0428) (end 40.15 -64.0428) (width 1.000001) (layer F.Cu) (net 302))
+  (segment (start 39 -64.825) (end 39.7822 -64.0428) (width 1) (layer F.Cu) (net 302))
+  (segment (start 39.7822 -64.0428) (end 40.15 -64.0428) (width 1) (layer F.Cu) (net 302))
   (segment (start 36.591 -60.4076) (end 36.591 -60.841) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 36.591 -60.841) (end 36.975 -61.225) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 44.6325 -74.8919) (end 45.4425 -74.8919) (width 0.15) (layer F.Cu) (net 302))
@@ -29082,8 +29082,8 @@
   (segment (start 28.2924 -45.355) (end 29.595 -45.355) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 29.595 -45.355) (end 29.6 -45.35) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 77.5726 -41.7274) (end 78.105 -41.7274) (width 0.299999) (layer F.Cu) (net 302))
-  (segment (start 69.4932 -77.9432) (end 69.725 -78.175) (width 0.599999) (layer F.Cu) (net 302))
-  (segment (start 69.725 -78.175) (end 70.45 -78.175) (width 0.599999) (layer F.Cu) (net 302))
+  (segment (start 69.4932 -77.9432) (end 69.725 -78.175) (width 0.6) (layer F.Cu) (net 302))
+  (segment (start 69.725 -78.175) (end 70.45 -78.175) (width 0.6) (layer F.Cu) (net 302))
   (segment (start 92.1004 -60.3264) (end 93.8892 -60.3264) (width 0.2) (layer F.Cu) (net 302))
   (segment (start 93.8892 -60.3264) (end 94.0562 -60.4934) (width 0.2) (layer F.Cu) (net 302))
   (segment (start 77.2908 -79.31861) (end 77.2908 -86.0908) (width 0.299999) (layer F.Cu) (net 302))
@@ -29093,8 +29093,8 @@
   (segment (start 77.0486 -76.9206) (end 77.0486 -78.1014) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 80.6958 -77.7366) (end 80.6958 -80.725) (width 0.299999) (layer F.Cu) (net 302))
   (segment (start 80.6958 -77.7366) (end 81.2074 -77.225) (width 0.299999) (layer F.Cu) (net 302))
-  (segment (start 69.625 -56.3) (end 69.625 -57.25) (width 1.000001) (layer F.Cu) (net 302))
-  (segment (start 69.625 -56.12499) (end 70.6 -56.12499) (width 1.000001) (layer F.Cu) (net 302))
+  (segment (start 69.625 -56.3) (end 69.625 -57.25) (width 1) (layer F.Cu) (net 302))
+  (segment (start 69.625 -56.12499) (end 70.6 -56.12499) (width 1) (layer F.Cu) (net 302))
 
   (zone (net 236) (net_name NetC117_1) (layer B.Cu) (tstamp 547BA6E6) (hatch edge 0.508)
     (priority 47)



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