[Cryptech-Commits] [core/hash/sha3] branch master updated: Adding functionality in sha3 tb to be able to build a baseline.
git at cryptech.is
git at cryptech.is
Tue Aug 23 12:26:47 UTC 2016
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joachim at secworks.se pushed a commit to branch master
in repository core/hash/sha3.
The following commit(s) were added to refs/heads/master by this push:
new 2130132 Adding functionality in sha3 tb to be able to build a baseline.
2130132 is described below
commit 2130132e85e41aecd35f88efef410f79c7a66246
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Tue Aug 23 14:26:36 2016 +0200
Adding functionality in sha3 tb to be able to build a baseline.
---
src/tb/tb_sha3.v | 178 ++++++++++++++++++++++++-------------------------------
1 file changed, 79 insertions(+), 99 deletions(-)
diff --git a/src/tb/tb_sha3.v b/src/tb/tb_sha3.v
index e15c9f1..95fe048 100644
--- a/src/tb/tb_sha3.v
+++ b/src/tb/tb_sha3.v
@@ -37,16 +37,7 @@
//
//======================================================================
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
-// Test module.
-//------------------------------------------------------------------
-module tb_sha256();
+module tb_sha3();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
@@ -60,21 +51,17 @@ module tb_sha256();
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
- reg [31 : 0] cycle_ctr;
- reg [31 : 0] error_ctr;
- reg [31 : 0] tc_ctr;
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
- reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
- wire tb_error;
-
- reg [31 : 0] read_data;
- reg [255 : 0] digest_data;
+ wire tb_ready;
//----------------------------------------------------------------
@@ -82,17 +69,13 @@ module tb_sha256();
//----------------------------------------------------------------
sha3 dut(
.clk(tb_clk),
- .reset_n(tb_reset_n),
-
- .cs(tb_cs),
- .we(tb_we),
-
-
- .address(tb_address),
- .write_data(tb_write_data),
- .read_data(tb_read_data),
- .error(tb_error)
- );
+ .nreset(tb_reset_n),
+ .w(tb_we),
+ .addr(tb_address[6 : 0]),
+ .din(tb_write_data),
+ .dout(tb_read_data),
+ .ready(tb_ready)
+ );
//----------------------------------------------------------------
@@ -120,11 +103,65 @@ module tb_sha256();
//----------------------------------------------------------------
+ // dump_state()
+ //
+ // Dump the internal state of the DUT.
+ //----------------------------------------------------------------
+ task dump_state;
+ begin
+ $display("State of the DUT");
+ $display("----------------");
+ $display("");
+ $display("st[00] = 0x%016x, st[01] = 0x%016x", dut.st[00], dut.st[01]);
+ $display("st[02] = 0x%016x, st[03] = 0x%016x", dut.st[02], dut.st[03]);
+ $display("st[04] = 0x%016x, st[05] = 0x%016x", dut.st[04], dut.st[05]);
+ $display("st[06] = 0x%016x, st[07] = 0x%016x", dut.st[06], dut.st[07]);
+ $display("st[08] = 0x%016x, st[09] = 0x%016x", dut.st[08], dut.st[09]);
+ $display("st[10] = 0x%016x, st[11] = 0x%016x", dut.st[10], dut.st[11]);
+ $display("st[12] = 0x%016x, st[13] = 0x%016x", dut.st[12], dut.st[13]);
+ $display("st[14] = 0x%016x, st[15] = 0x%016x", dut.st[14], dut.st[15]);
+ $display("st[16] = 0x%016x, st[17] = 0x%016x", dut.st[16], dut.st[17]);
+ $display("st[18] = 0x%016x, st[19] = 0x%016x", dut.st[18], dut.st[19]);
+ $display("st[20] = 0x%016x, st[21] = 0x%016x", dut.st[20], dut.st[21]);
+ $display("st[22] = 0x%016x, st[23] = 0x%016x", dut.st[22], dut.st[23]);
+ $display("st[24] = 0x%016x", dut.st[24]);
+ $display("");
+
+ $display("stn[00] = 0x%016x, stn[01] = 0x%016x", dut.stn[00], dut.stn[01]);
+ $display("stn[02] = 0x%016x, stn[03] = 0x%016x", dut.stn[02], dut.stn[03]);
+ $display("stn[04] = 0x%016x, stn[05] = 0x%016x", dut.stn[04], dut.stn[05]);
+ $display("stn[06] = 0x%016x, stn[07] = 0x%016x", dut.stn[06], dut.stn[07]);
+ $display("stn[08] = 0x%016x, stn[09] = 0x%016x", dut.stn[08], dut.stn[09]);
+ $display("stn[10] = 0x%016x, stn[11] = 0x%016x", dut.stn[10], dut.stn[11]);
+ $display("stn[12] = 0x%016x, stn[13] = 0x%016x", dut.stn[12], dut.stn[13]);
+ $display("stn[14] = 0x%016x, stn[15] = 0x%016x", dut.stn[14], dut.stn[15]);
+ $display("stn[16] = 0x%016x, stn[17] = 0x%016x", dut.stn[16], dut.stn[17]);
+ $display("stn[18] = 0x%016x, stn[19] = 0x%016x", dut.stn[18], dut.stn[19]);
+ $display("stn[20] = 0x%016x, stn[21] = 0x%016x", dut.stn[20], dut.stn[21]);
+ $display("stn[22] = 0x%016x, stn[23] = 0x%016x", dut.stn[22], dut.stn[23]);
+ $display("stn[24] = 0x%016x", dut.stn[24]);
+ $display("");
+
+ $display("bc[00] = 0x%016x, bc[01] = 0x%016x", dut.bc[00], dut.bc[01]);
+ $display("bc[02] = 0x%016x, bc[03] = 0x%016x", dut.bc[02], dut.bc[03]);
+ $display("bc[04] = 0x%016x", dut.stn[04]);
+ $display("");
+
+ $display("t = 0x%016x", dut.t);
+ $display("");
+
+ $display("round = 0x%04x, roundlimit = 0x%04x", dut.round, dut.roundlimit);
+ $display("");
+ end
+ endtask // dump_state
+
+
+ //----------------------------------------------------------------
// reset_dut()
//
// Toggles reset to force the DUT into a well defined state.
//----------------------------------------------------------------
- task reset_dut();
+ task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
@@ -140,18 +177,15 @@ module tb_sha256();
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
- task init_sim();
+ task init_sim;
begin
- cycle_ctr = 32'h00000000;
- error_ctr = 32'h00000000;
- tc_ctr = 32'h00000000;
+ cycle_ctr = 32'h0;
tb_clk = 0;
tb_reset_n = 0;
- tb_cs = 0;
tb_we = 0;
- tb_address = 6'h00;
- tb_write_data = 32'h00000000;
+ tb_address = 6'h0;
+ tb_write_data = 32'h0;
end
endtask // init_dut
@@ -161,7 +195,7 @@ module tb_sha256();
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_result();
+ task display_test_result;
begin
if (error_ctr == 0)
begin
@@ -177,63 +211,16 @@ module tb_sha256();
//----------------------------------------------------------------
- // wait_ready()
+ // simple_test()
//
- // Wait for the ready flag in the dut to be set.
- // (Actually we wait for either ready or valid to be set.)
- //
- // Note: It is the callers responsibility to call the function
- // when the dut is actively processing and will in fact at some
- // point set the flag.
+ // A first simple test that verifies what happens with an all
+ // zero data input.
//----------------------------------------------------------------
- task wait_ready();
+ task simple_test;
begin
- read_data = 0;
-
- while (read_data == 0)
- begin
- read_word(ADDR_STATUS);
- end
+ dump_state();
end
- endtask // wait_ready
-
-
- //----------------------------------------------------------------
- // single_block_test()
- //
- //
- // Perform test of a single block digest.
- //----------------------------------------------------------------
- task single_block_test(input [511 : 0] block,
- input [255 : 0] expected);
- begin
- $display("*** TC%01d - Single block test started.", tc_ctr);
-
- $display("*** TC%01d - Single block test done.", tc_ctr);
- tc_ctr = tc_ctr + 1;
- end
- endtask // single_block_test
-
-
- //----------------------------------------------------------------
- // double_block_test()
- //
- //
- // Perform test of a double block digest. Note that we check
- // the digests for both the first and final block.
- //----------------------------------------------------------------
- task double_block_test(input [511 : 0] block0,
- input [255 : 0] expected0,
- input [511 : 0] block1,
- input [255 : 0] expected1
- );
- begin
- $display("*** TC%01d - Double block test started.", tc_ctr);
-
- $display("*** TC%01d - Double block test done.", tc_ctr);
- tc_ctr = tc_ctr + 1;
- end
- endtask // double_block_test
+ endtask // simple_test
//----------------------------------------------------------------
@@ -242,18 +229,11 @@ module tb_sha256();
//----------------------------------------------------------------
initial
begin : sha3_test
- reg [511 : 0] tc0;
- reg [255 : 0] res0;
-
- reg [511 : 0] tc1_0;
- reg [255 : 0] res1_0;
- reg [511 : 0] tc1_1;
- reg [255 : 0] res1_1;
-
$display(" -- Testbench for sha3 started --");
init_sim();
reset_dut();
+ simple_test();
$display(" -- Testbench for sha3 done. --");
$finish;
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