[Cryptech-Commits] [core/rng/trng] 03/04: (1) Debugged the block stat counter. (2) Added missing port type. (3) Removed second define for default number of blocks.

[git at cryptech.is]

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joachim at secworks.se pushed a commit to branch master
in repository core/rng/trng.

commit cf512b20d938fb36eb987d90d6ada7830ff42002
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Mon Sep 7 12:29:52 2015 +0200

    (1) Debugged the block stat counter. (2) Added missing port type. (3) Removed second define for default number of blocks.
---
 src/rtl/trng_csprng.v | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index ce5b50f..d33e72a 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -49,7 +49,7 @@ module trng_csprng(
                    output wire          error,
 
                    input wire           discard,
-                   input                test_mode,
+                   input wire           test_mode,
                    output wire          more_seed,
                    output wire          security_error,
 
@@ -118,7 +118,6 @@ module trng_csprng(
   localparam CTRL_CANCEL = 4'hf;
 
   localparam DEFAULT_NUM_ROUNDS = 5'h18;
-  localparam DEFAULT_NUM_BLOCKS = 64'h1000000000000000;
   localparam DEFAULT_NUM_BLOCKS = 64'h0000000001000000;
 
   parameter CORE_NAME0     = 32'h63737072; // "cspr"
@@ -154,6 +153,7 @@ module trng_csprng(
 
   reg [63 : 0]  block_stat_ctr_reg;
   reg [63 : 0]  block_stat_ctr_new;
+  reg           block_stat_ctr_we;
 
   reg [31 : 0]  reseed_stat_ctr_reg;
   reg [31 : 0]  reseed_stat_ctr_new;
@@ -321,6 +321,10 @@ module trng_csprng(
           if (block_ctr_we)
             begin
               block_ctr_reg      <= block_ctr_new;
+            end
+
+          if (block_stat_ctr_we)
+            begin
               block_stat_ctr_reg <= block_stat_ctr_new;
             end
 
@@ -479,6 +483,7 @@ module trng_csprng(
       block_ctr_we       = 1'b0;
       block_ctr_max      = 1'b0;
       block_stat_ctr_new = {2{32'h00000000}};
+      block_stat_ctr_we = 1'b0;
 
       if (block_ctr_rst)
         begin
@@ -489,8 +494,9 @@ module trng_csprng(
       if (block_ctr_inc)
         begin
           block_ctr_new      = block_ctr_reg + 1'b1;
-          block_stat_ctr_new = block_stat_ctr_reg + 1'b1;
           block_ctr_we       = 1;
+          block_stat_ctr_new = block_stat_ctr_reg + 1'b1;
+          block_stat_ctr_we  = 1;
         end
 
       if ((block_ctr_reg == {num_blocks_high_reg, num_blocks_low_reg}) ||