[Cryptech-Commits] [core/cipher/aes] 01/02: Removed api error port and added error bit in status register that is set when api access violations happens and cleared by writing the status register.

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joachim at secworks.se pushed a commit to branch api_error_fix
in repository core/cipher/aes.

commit 28a9cddf2fa7e934ea790b0e59fcbeddf0c125bc
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Fri Oct 2 15:39:34 2015 +0200

    Removed api error port and added error bit in status register that is set when api access violations happens and cleared by writing the status register.
---
 src/rtl/aes.v   | 34 +++++++++++++++++++++++++---------
 src/tb/tb_aes.v |  4 +---
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/rtl/aes.v b/src/rtl/aes.v
index 98fe61a..7b422b5 100644
--- a/src/rtl/aes.v
+++ b/src/rtl/aes.v
@@ -48,8 +48,7 @@ module aes(
            // Data ports.
            input wire  [7 : 0]  address,
            input wire  [31 : 0] write_data,
-           output wire [31 : 0] read_data,
-           output wire          error
+           output wire [31 : 0] read_data
           );
 
   //----------------------------------------------------------------
@@ -66,6 +65,7 @@ module aes(
   localparam ADDR_STATUS      = 8'h09;
   localparam STATUS_READY_BIT = 0;
   localparam STATUS_VALID_BIT = 1;
+  localparam STATUS_ERROR_BIT = 2;
 
   localparam ADDR_CONFIG      = 8'h0a;
   localparam CTRL_ENCDEC_BIT  = 0;
@@ -92,7 +92,7 @@ module aes(
 
   localparam CORE_NAME0       = 32'h61657320; // "aes "
   localparam CORE_NAME1       = 32'h20202020; // "    "
-  localparam CORE_VERSION     = 32'h302e3830; // "0.80"
+  localparam CORE_VERSION     = 32'h302e3831; // "0.81"
 
 
   //----------------------------------------------------------------
@@ -108,6 +108,10 @@ module aes(
   reg next_we;
   reg next_set;
 
+  reg error_reg;
+  reg error_new;
+  reg error_we;
+
   reg encdec_reg;
   reg keylen_reg;
   reg config_we;
@@ -147,7 +151,6 @@ module aes(
   // Wires.
   //----------------------------------------------------------------
   reg [31 : 0]   tmp_read_data;
-  reg            tmp_error;
 
   wire           core_encdec;
   wire           core_init;
@@ -164,7 +167,6 @@ module aes(
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
   assign read_data = tmp_read_data;
-  assign error     = tmp_error;
 
   assign core_key = {key0_reg, key1_reg, key2_reg, key3_reg,
                      key4_reg, key5_reg, key6_reg, key7_reg};
@@ -226,6 +228,8 @@ module aes(
           encdec_reg <= 0;
           keylen_reg <= 0;
 
+          error_reg  <= 0;
+
           result_reg <= 128'h00000000000000000000000000000000;
           valid_reg  <= 0;
           ready_reg  <= 0;
@@ -236,6 +240,9 @@ module aes(
           valid_reg      <= core_valid;
           result_reg     <= core_result;
 
+          if (error_we)
+            error_reg <= error_new;
+
           if (init_we)
             begin
               init_reg <= init_new;
@@ -362,6 +369,8 @@ module aes(
       init_set      = 0;
       next_set      = 0;
       config_we     = 0;
+      error_new     = 0;
+      error_we      = 0;
       key0_we       = 0;
       key1_we       = 0;
       key2_we       = 0;
@@ -375,7 +384,6 @@ module aes(
       block2_we     = 0;
       block3_we     = 0;
       tmp_read_data = 32'h00000000;
-      tmp_error     = 0;
 
       if (cs)
         begin
@@ -389,6 +397,12 @@ module aes(
                     next_set = write_data[CTRL_NEXT_BIT];
                   end
 
+                ADDR_STATUS:
+                  begin
+                    error_new = 0;
+                    error_we  = 1;
+                  end
+
                 ADDR_CONFIG:
                   begin
                     config_we = 1;
@@ -456,7 +470,8 @@ module aes(
 
                 default:
                   begin
-                    tmp_error = 1;
+                    error_new = 1;
+                    error_we  = 1;
                   end
               endcase // case (address)
             end // if (we)
@@ -488,7 +503,7 @@ module aes(
 
                 ADDR_STATUS:
                   begin
-                    tmp_read_data = {30'h00000000, valid_reg, ready_reg};
+                    tmp_read_data = {29'h00000000, error_reg, valid_reg, ready_reg};
                   end
 
                 ADDR_KEY0:
@@ -573,7 +588,8 @@ module aes(
 
                 default:
                   begin
-                    tmp_error = 1;
+                    error_new = 1;
+                    error_we  = 1;
                   end
               endcase // case (address)
             end
diff --git a/src/tb/tb_aes.v b/src/tb/tb_aes.v
index 0694250..377ed76 100644
--- a/src/tb/tb_aes.v
+++ b/src/tb/tb_aes.v
@@ -115,7 +115,6 @@ module tb_aes();
   reg [7  : 0]  tb_address;
   reg [31 : 0]  tb_write_data;
   wire [31 : 0] tb_read_data;
-  wire          tb_error;
 
 
   //----------------------------------------------------------------
@@ -128,8 +127,7 @@ module tb_aes();
            .we(tb_we),
            .address(tb_address),
            .write_data(tb_write_data),
-           .read_data(tb_read_data),
-           .error(tb_error)
+           .read_data(tb_read_data)
           );