[Cryptech-Commits] [core/platform/novena] 04/07: Merge branch 'config_core_selector'

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paul at psgd.org pushed a commit to branch master
in repository core/platform/novena.

commit b1e661bf4f8a715743222977067c1cf560408b40
Merge: 5ad8554 47508ec
Author: Paul Selkirk <paul at psgd.org>
Date:   Fri Nov 13 17:03:52 2015 -0500

    Merge branch 'config_core_selector'

 common/rtl/lint-dummy.v  |  14 +-
 common/rtl/novena_regs.v |   4 +-
 config/config.cfg        | 128 +++++++++++
 config/config.py         | 543 +++++++++++++++++++++++++++++++++++++++++++++++
 config/core_selector.v   | 279 ++++++++++++++++++++++++
 config/core_vfiles.mk    |  42 ++++
 eim/build/Makefile       | 110 ++++------
 eim/build/xilinx.mk      |  16 +-
 eim/rtl/novena_eim.v     |   4 +-
 fmc/build/Makefile       | 109 ++++------
 i2c/build/Makefile       | 102 ++++-----
 i2c/build/xilinx.mk      |  16 +-
 i2c/rtl/novena_i2c.v     |  14 +-
 sw/Makefile              |   2 +-
 sw/Makefile.i2c          |   2 +-
 sw/aes_tester.c          | 102 +++++----
 sw/capability.c          | 145 +++++++++++++
 sw/configure-fpga.sh     |   6 +-
 sw/cryptech.h            | 405 +++++++++++++++++------------------
 sw/hash.c                |  84 ++++++--
 sw/hash_tester.c         | 206 +++++++++++++-----
 sw/modexp_tester.c       | 333 ++++++++++++++---------------
 sw/modexps6_tester.c     | 224 +++++++++----------
 sw/novena-eim.c          |  16 +-
 sw/tc_eim.c              |  28 +--
 sw/tc_i2c.c              |   6 +-
 sw/trng_extractor.c      |  58 ++---
 sw/trng_tester.c         | 119 +++++++++--
 28 files changed, 2171 insertions(+), 946 deletions(-)

diff --cc eim/build/Makefile
index 678a2e5,630faa9..a7eec60
--- a/eim/build/Makefile
+++ b/eim/build/Makefile
@@@ -1,72 -1,42 +1,42 @@@
- project = novena_eim
- vendor = xilinx
- family = spartan6
- part = xc6slx45csg324-3
- top_module = novena_top
- isedir = /opt/Xilinx/14.7/ISE_DS
- xil_env = . $(isedir)/settings64.sh
- ucf = ../ucf/novena_eim.ucf
+ # Localize all the relative path awfulness in one variable.
+ 
+ CORE_TREE	:= $(abspath ../../../..)
+ 
+ # Figure out what the native word size is on the build host, because
+ # the XiLinx tools care for some reason.
+ 
+ WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+ 
 -# Parameters to xilinkx.mk.
++# Parameters to xilinx.mk.
+ 
+ project		= novena_eim
+ vendor		= xilinx
+ family		= spartan6
+ part		= xc6slx45csg324-3
+ top_module	= novena_top
+ isedir		= /opt/Xilinx/14.7/ISE_DS
+ xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
+ ucf		= ../ucf/$(project).ucf
+ 
+ # Verilog files that always go with builds on this platform.
  
  vfiles = \
- 	../rtl/novena_eim.v \
- 	../../common/rtl/novena_regs.v \
- 	../../common/rtl/novena_clkmgr.v \
- 	../../common/rtl/clkmgr_dcm.v \
- 	../../../common/core_selector/src/rtl/core_selector.v \
- 	../../../common/core_selector/src/rtl/global_selector.v \
- 	../../../common/core_selector/src/rtl/hash_selector.v \
- 	../../../common/core_selector/src/rtl/rng_selector.v \
- 	../../../common/core_selector/src/rtl/cipher_selector.v \
- 	../../../common/core_selector/src/rtl/math_selector.v \
- 	../../../../comm/eim/src/rtl/cdc_bus_pulse.v \
- 	../../../../comm/eim/src/rtl/eim_arbiter_cdc.v \
- 	../../../../comm/eim/src/rtl/eim_arbiter.v \
- 	../../../../comm/eim/src/rtl/eim_da_phy.v \
- 	../../../../comm/eim/src/rtl/eim_indicator.v \
- 	../../../../comm/eim/src/rtl/eim_regs.v \
- 	../../../../comm/eim/src/rtl/eim.v \
- 	../../../../hash/sha1/src/rtl/sha1.v \
- 	../../../../hash/sha1/src/rtl/sha1_core.v \
- 	../../../../hash/sha1/src/rtl/sha1_w_mem.v \
- 	../../../../hash/sha256/src/rtl/sha256.v \
- 	../../../../hash/sha256/src/rtl/sha256_core.v \
- 	../../../../hash/sha256/src/rtl/sha256_k_constants.v \
- 	../../../../hash/sha256/src/rtl/sha256_w_mem.v \
- 	../../../../hash/sha512/src/rtl/sha512.v \
- 	../../../../hash/sha512/src/rtl/sha512_core.v \
- 	../../../../hash/sha512/src/rtl/sha512_h_constants.v \
- 	../../../../hash/sha512/src/rtl/sha512_k_constants.v \
- 	../../../../hash/sha512/src/rtl/sha512_w_mem.v \
- 	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
- 	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
- 	../../../../rng/rosc_entropy/src/rtl/rosc.v \
- 	../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
- 	../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
- 	../../../../rng/trng/src/rtl/trng.v \
- 	../../../../rng/trng/src/rtl/trng_csprng.v \
- 	../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
- 	../../../../rng/trng/src/rtl/trng_mixer.v \
- 	../../../../cipher/aes/src/rtl/aes.v \
- 	../../../../cipher/aes/src/rtl/aes_core.v \
- 	../../../../cipher/aes/src/rtl/aes_decipher_block.v \
- 	../../../../cipher/aes/src/rtl/aes_encipher_block.v \
- 	../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
- 	../../../../cipher/aes/src/rtl/aes_key_mem.v \
- 	../../../../cipher/aes/src/rtl/aes_sbox.v \
- 	../../../../cipher/chacha/src/rtl/chacha.v \
- 	../../../../cipher/chacha/src/rtl/chacha_core.v \
- 	../../../../cipher/chacha/src/rtl/chacha_qr.v \
- 	../../../../math/modexps6/src/rtl/modexps6_adder64_carry32.v \
- 	../../../../math/modexps6/src/rtl/modexps6_buffer_core.v \
- 	../../../../math/modexps6/src/rtl/modexps6_buffer_user.v \
- 	../../../../math/modexps6/src/rtl/modexps6_modinv32.v \
- 	../../../../math/modexps6/src/rtl/modexps6_montgomery_coeff.v \
- 	../../../../math/modexps6/src/rtl/modexps6_montgomery_multiplier.v \
- 	../../../../math/modexps6/src/rtl/modexps6_top.v \
- 	../../../../math/modexps6/src/rtl/modexps6_wrapper.v \
- 	../../../../math/modexps6/src/rtl/ram_1rw_1ro_readfirst.v \
- 	../../../../math/modexps6/src/rtl/ipcore/multiplier_s6.v \
- 	../../../../math/modexps6/src/rtl/ipcore/subtractor_s6.v
+ 	$(CORE_TREE)/platform/novena/eim/rtl/novena_eim.v \
+ 	$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
+ 	$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
 -	$(CORE_TREE)/platform/novena/common/rtl/ipcore/clkmgr_dcm.v \
++	$(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
+ 	$(CORE_TREE)/platform/novena/config/core_selector.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/eim_da_phy.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/eim_indicator.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/eim_regs.v \
+ 	$(CORE_TREE)/comm/eim/src/rtl/eim.v
+ 
+ # Verilog files selected by the core configuration script.
+ 
+ -include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
  
  include xilinx.mk
  
diff --cc fmc/build/Makefile
index 7c73c89,630faa9..81a43d0
--- a/fmc/build/Makefile
+++ b/fmc/build/Makefile
@@@ -1,70 -1,48 +1,47 @@@
- project = novena_fmc
- vendor = xilinx
- family = spartan6
- part = xc6slx45csg324-3
- top_module = novena_fmc_top
- isedir = /opt/Xilinx/14.7/ISE_DS
- xil_env = . $(isedir)/settings64.sh
- ucf = ../ucf/$(project).ucf
+ # Localize all the relative path awfulness in one variable.
+ 
+ CORE_TREE	:= $(abspath ../../../..)
+ 
+ # Figure out what the native word size is on the build host, because
+ # the XiLinx tools care for some reason.
+ 
+ WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+ 
 -# Parameters to xilinkx.mk.
++# Parameters to xilinx.mk.
+ 
 -project		= novena_eim
++project		= novena_fmc
+ vendor		= xilinx
+ family		= spartan6
+ part		= xc6slx45csg324-3
+ top_module	= novena_top
+ isedir		= /opt/Xilinx/14.7/ISE_DS
+ xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
+ ucf		= ../ucf/$(project).ucf
+ 
+ # Verilog files that always go with builds on this platform.
  
  vfiles = \
- 	../rtl/novena_fmc_top.v \
- 	../../common/rtl/novena_regs.v \
- 	../../common/rtl/novena_clkmgr.v \
- 	../../common/rtl/clkmgr_dcm.v \
- 	../../../common/core_selector/src/rtl/core_selector.v \
- 	../../../common/core_selector/src/rtl/global_selector.v \
- 	../../../common/core_selector/src/rtl/hash_selector.v \
- 	../../../common/core_selector/src/rtl/rng_selector.v \
- 	../../../common/core_selector/src/rtl/cipher_selector.v \
- 	../../../common/core_selector/src/rtl/math_selector.v \
- 	../../../../comm/fmc/src/rtl/cdc_bus_pulse.v \
- 	../../../../comm/fmc/src/rtl/fmc_arbiter_cdc.v \
- 	../../../../comm/fmc/src/rtl/fmc_arbiter.v \
- 	../../../../comm/fmc/src/rtl/fmc_d_phy.v \
- 	../../../../comm/fmc/src/rtl/fmc_indicator.v \
- 	../../../../comm/fmc/src/rtl/fmc_regs.v \
- 	../../../../hash/sha1/src/rtl/sha1.v \
- 	../../../../hash/sha1/src/rtl/sha1_core.v \
- 	../../../../hash/sha1/src/rtl/sha1_w_mem.v \
- 	../../../../hash/sha256/src/rtl/sha256.v \
- 	../../../../hash/sha256/src/rtl/sha256_core.v \
- 	../../../../hash/sha256/src/rtl/sha256_k_constants.v \
- 	../../../../hash/sha256/src/rtl/sha256_w_mem.v \
- 	../../../../hash/sha512/src/rtl/sha512.v \
- 	../../../../hash/sha512/src/rtl/sha512_core.v \
- 	../../../../hash/sha512/src/rtl/sha512_h_constants.v \
- 	../../../../hash/sha512/src/rtl/sha512_k_constants.v \
- 	../../../../hash/sha512/src/rtl/sha512_w_mem.v \
- 	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
- 	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
- 	../../../../rng/rosc_entropy/src/rtl/rosc.v \
- 	../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
- 	../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
- 	../../../../rng/trng/src/rtl/trng.v \
- 	../../../../rng/trng/src/rtl/trng_csprng.v \
- 	../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
- 	../../../../rng/trng/src/rtl/trng_mixer.v \
- 	../../../../cipher/aes/src/rtl/aes.v \
- 	../../../../cipher/aes/src/rtl/aes_core.v \
- 	../../../../cipher/aes/src/rtl/aes_decipher_block.v \
- 	../../../../cipher/aes/src/rtl/aes_encipher_block.v \
- 	../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
- 	../../../../cipher/aes/src/rtl/aes_key_mem.v \
- 	../../../../cipher/aes/src/rtl/aes_sbox.v \
- 	../../../../cipher/chacha/src/rtl/chacha.v \
- 	../../../../cipher/chacha/src/rtl/chacha_core.v \
- 	../../../../cipher/chacha/src/rtl/chacha_qr.v \
- 	../../../../math/modexp/src/rtl/adder.v \
- 	../../../../math/modexp/src/rtl/blockmem1r1w.v \
- 	../../../../math/modexp/src/rtl/blockmem2r1wptr.v \
- 	../../../../math/modexp/src/rtl/blockmem2r1w.v \
- 	../../../../math/modexp/src/rtl/blockmem2rptr1w.v \
- 	../../../../math/modexp/src/rtl/modexp.v \
- 	../../../../math/modexp/src/rtl/modexp_core.v \
- 	../../../../math/modexp/src/rtl/montprod.v \
- 	../../../../math/modexp/src/rtl/residue.v \
- 	../../../../math/modexp/src/rtl/shl.v \
- 	../../../../math/modexp/src/rtl/shr.v
 -	$(CORE_TREE)/platform/novena/eim/rtl/novena_eim.v \
++	$(CORE_TREE)/platform/novena/fmc/rtl/novena_fmc_top.v \
+ 	$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
+ 	$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
 -	$(CORE_TREE)/platform/novena/common/rtl/ipcore/clkmgr_dcm.v \
++	$(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
+ 	$(CORE_TREE)/platform/novena/config/core_selector.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/cdc_bus_pulse.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter_cdc.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/eim_arbiter.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/eim_da_phy.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/eim_indicator.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/eim_regs.v \
 -	$(CORE_TREE)/comm/eim/src/rtl/eim.v
++	$(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
++	$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
++	$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
++	$(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
++	$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
++	$(CORE_TREE)/comm/fmc/src/rtl/fmc_regs.v
+ 
+ # Verilog files selected by the core configuration script.
+ 
+ -include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
  
  include xilinx.mk
+ 
+ # Fun extras for running verlator as a linter.
+ 
+ VERILATOR_FLAGS	= --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
+ 
+ lint:
+ 	verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v
diff --cc i2c/build/Makefile
index 1859da3,1859da3..441b67a
--- a/i2c/build/Makefile
+++ b/i2c/build/Makefile
@@@ -1,70 -1,70 +1,44 @@@
--project = novena_i2c
--vendor = xilinx
--family = spartan6
--part = xc6slx45csg324-3
--top_module = novena_top
--isedir = /opt/Xilinx/14.7/ISE_DS
--xil_env = . $(isedir)/settings64.sh
--ucf = ../ucf/novena_i2c.ucf
++# Localize all the relative path awfulness in one variable.
++
++CORE_TREE	:= $(abspath ../../../..)
++
++# Figure out what the native word size is on the build host, because
++# the XiLinx tools care for some reason.
++
++WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
++
++# Parameters to xilinx.mk.
++
++project		= novena_eim
++vendor		= xilinx
++family		= spartan6
++part		= xc6slx45csg324-3
++top_module	= novena_top
++isedir		= /opt/Xilinx/14.7/ISE_DS
++xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
++ucf		= ../ucf/$(project).ucf
++
++# Verilog files that always go with builds on this platform.
  
  vfiles = \
--	../rtl/novena_i2c.v \
--	../../common/rtl/novena_regs.v \
--	../../common/rtl/novena_clkmgr.v \
--	../../common/rtl/ipcore/clkmgr_dcm.v \
--	../../../common/core_selector/src/rtl/core_selector.v \
--	../../../common/core_selector/src/rtl/global_selector.v \
--	../../../common/core_selector/src/rtl/hash_selector.v \
--	../../../common/core_selector/src/rtl/rng_selector.v \
--	../../../common/core_selector/src/rtl/cipher_selector.v \
--	../../../common/core_selector/src/rtl/math_selector.v \
--	../../../../comm/i2c/src/rtl/i2c_regs.v \
--	../../../../comm/i2c/src/rtl/i2c_core.v \
--	../../../../comm/coretest/src/rtl/coretest.v \
--	../../../../hash/sha1/src/rtl/sha1.v \
--	../../../../hash/sha1/src/rtl/sha1_core.v \
--	../../../../hash/sha1/src/rtl/sha1_w_mem.v \
--	../../../../hash/sha256/src/rtl/sha256.v \
--	../../../../hash/sha256/src/rtl/sha256_core.v \
--	../../../../hash/sha256/src/rtl/sha256_k_constants.v \
--	../../../../hash/sha256/src/rtl/sha256_w_mem.v \
--	../../../../hash/sha512/src/rtl/sha512.v \
--	../../../../hash/sha512/src/rtl/sha512_core.v \
--	../../../../hash/sha512/src/rtl/sha512_h_constants.v \
--	../../../../hash/sha512/src/rtl/sha512_k_constants.v \
--	../../../../hash/sha512/src/rtl/sha512_w_mem.v \
--	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy.v \
--	../../../../rng/avalanche_entropy/src/rtl/avalanche_entropy_core.v \
--	../../../../rng/rosc_entropy/src/rtl/rosc.v \
--	../../../../rng/rosc_entropy/src/rtl/rosc_entropy.v \
--	../../../../rng/rosc_entropy/src/rtl/rosc_entropy_core.v \
--	../../../../rng/trng/src/rtl/trng.v \
--	../../../../rng/trng/src/rtl/trng_csprng.v \
--	../../../../rng/trng/src/rtl/trng_csprng_fifo.v \
--	../../../../rng/trng/src/rtl/trng_mixer.v \
--	../../../../cipher/aes/src/rtl/aes.v \
--	../../../../cipher/aes/src/rtl/aes_core.v \
--	../../../../cipher/aes/src/rtl/aes_decipher_block.v \
--	../../../../cipher/aes/src/rtl/aes_encipher_block.v \
--	../../../../cipher/aes/src/rtl/aes_inv_sbox.v \
--	../../../../cipher/aes/src/rtl/aes_key_mem.v \
--	../../../../cipher/aes/src/rtl/aes_sbox.v \
--	../../../../cipher/chacha/src/rtl/chacha.v \
--	../../../../cipher/chacha/src/rtl/chacha_core.v \
--	../../../../cipher/chacha/src/rtl/chacha_qr.v \
--	../../../../math/modexp/src/rtl/adder32.v \
--	../../../../math/modexp/src/rtl/blockmem1r1w.v \
--	../../../../math/modexp/src/rtl/blockmem2r1wptr.v \
--	../../../../math/modexp/src/rtl/blockmem2r1w.v \
--	../../../../math/modexp/src/rtl/blockmem2rptr1w.v \
--	../../../../math/modexp/src/rtl/modexp.v \
--	../../../../math/modexp/src/rtl/modexp_core.v \
--	../../../../math/modexp/src/rtl/montprod.v \
--	../../../../math/modexp/src/rtl/residue.v \
--	../../../../math/modexp/src/rtl/shl32.v \
--	../../../../math/modexp/src/rtl/shr32.v
++	$(CORE_TREE)/platform/novena/i2c/rtl/novena_i2c.v \
++	$(CORE_TREE)/platform/novena/common/rtl/novena_regs.v \
++	$(CORE_TREE)/platform/novena/common/rtl/novena_clkmgr.v \
++	$(CORE_TREE)/platform/novena/common/rtl/clkmgr_dcm.v \
++	$(CORE_TREE)/platform/novena/config/core_selector.v \
++	$(CORE_TREE)/comm/i2c/src/rtl/i2c_regs.v \
++	$(CORE_TREE)/comm/i2c/src/rtl/i2c_core.v \
++	$(CORE_TREE)/comm/coretest/src/rtl/coretest.v
++
++# Verilog files selected by the core configuration script.
++
++-include $(CORE_TREE)/platform/novena/config/core_vfiles.mk
  
  include xilinx.mk
  
++# Fun extras for running verlator as a linter.
++
++VERILATOR_FLAGS	= --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME
++
  lint:
--	verilator --lint-only --top-module novena_top -Wall -Wno-fatal -Wno-DECLFILENAME $(vfiles) ../../common/rtl/lint-dummy.v
++	verilator ${VERILATOR_FLAGS} $(vfiles) $(CORE_TREE)/platform/novena/common/rtl/lint-dummy.v
diff --cc i2c/rtl/novena_i2c.v
index 4ea6f82,f6230a0..db2c203
--- a/i2c/rtl/novena_i2c.v
+++ b/i2c/rtl/novena_i2c.v
@@@ -99,8 -94,9 +99,8 @@@ module novena_to
  
     wire 		sda_pd;
     wire 		sda_int;
-    
+ 
     wire 		clk = sys_clk;
 -   wire 		reset_n = ~sys_rst;
  
     // Coretest connections.
     wire 		coretest_reset_n;
@@@ -153,8 -149,8 +153,8 @@@
     coretest coretest
       (
        .clk(clk),
 -      .reset_n(reset_n),
 +      .reset_n(sys_rst_n),
-       
+ 
        .rx_syn(i2c_rxd_syn),
        .rx_data(i2c_rxd_data),
        .rx_ack(i2c_rxd_ack),
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