[Cryptech-Commits] [core/platform/novena] 01/01: (1) Added base address to all AES addresses. (2) Added base address to all ChaCha addresses. (3) Updated modexp addresses with new memory access ports. Removed all prefixes that are now redundant. Fixed minor modexp mapping nits such as incorrect order of length addresses. Updated the version to reflect changes of API and that we now can do trivial modexp operations from SW.
git at cryptech.is
git at cryptech.is
Wed May 13 15:11:12 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository core/platform/novena.
commit f2164aa044c4166b918fc7b3c51d4c9a0755de47
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Wed May 13 17:11:00 2015 +0200
(1) Added base address to all AES addresses. (2) Added base address to all ChaCha addresses. (3) Updated modexp addresses with new memory access ports. Removed all prefixes that are now redundant. Fixed minor modexp mapping nits such as incorrect order of length addresses. Updated the version to reflect changes of API and that we now can do trivial modexp operations from SW.
---
sw/cryptech.h | 178 ++++++++++++++++++++++++++++++----------------------------
1 file changed, 91 insertions(+), 87 deletions(-)
diff --git a/sw/cryptech.h b/sw/cryptech.h
index 05862bb..5b01bc9 100644
--- a/sw/cryptech.h
+++ b/sw/cryptech.h
@@ -295,24 +295,24 @@ in order to map it into a 16-bit address space.
#define AES_CONFIG_ENCDEC 1
#define AES_CONFIG_KEYLEN 2
-#define AES_ADDR_KEY0 0x10
-#define AES_ADDR_KEY1 0x11
-#define AES_ADDR_KEY2 0x12
-#define AES_ADDR_KEY3 0x13
-#define AES_ADDR_KEY4 0x14
-#define AES_ADDR_KEY5 0x15
-#define AES_ADDR_KEY6 0x16
-#define AES_ADDR_KEY7 0x17
-
-#define AES_ADDR_BLOCK0 0x20
-#define AES_ADDR_BLOCK1 0x21
-#define AES_ADDR_BLOCK2 0x22
-#define AES_ADDR_BLOCK3 0x23
-
-#define AES_ADDR_RESULT0 0x30
-#define AES_ADDR_RESULT1 0x31
-#define AES_ADDR_RESULT2 0x32
-#define AES_ADDR_RESULT3 0x33
+#define AES_ADDR_KEY0 AES_ADDR_BASE + 0x10
+#define AES_ADDR_KEY1 AES_ADDR_BASE + 0x11
+#define AES_ADDR_KEY2 AES_ADDR_BASE + 0x12
+#define AES_ADDR_KEY3 AES_ADDR_BASE + 0x13
+#define AES_ADDR_KEY4 AES_ADDR_BASE + 0x14
+#define AES_ADDR_KEY5 AES_ADDR_BASE + 0x15
+#define AES_ADDR_KEY6 AES_ADDR_BASE + 0x16
+#define AES_ADDR_KEY7 AES_ADDR_BASE + 0x17
+
+#define AES_ADDR_BLOCK0 AES_ADDR_BASE + 0x20
+#define AES_ADDR_BLOCK1 AES_ADDR_BASE + 0x21
+#define AES_ADDR_BLOCK2 AES_ADDR_BASE + 0x22
+#define AES_ADDR_BLOCK3 AES_ADDR_BASE + 0x23
+
+#define AES_ADDR_RESULT0 AES_ADDR_BASE + 0x30
+#define AES_ADDR_RESULT1 AES_ADDR_BASE + 0x31
+#define AES_ADDR_RESULT2 AES_ADDR_BASE + 0x32
+#define AES_ADDR_RESULT3 AES_ADDR_BASE + 0x33
// current name and version values
#define AES_CORE_NAME0 "aes "
@@ -328,56 +328,56 @@ in order to map it into a 16-bit address space.
#define CHACHA_ADDR_CTRL CHACHA_ADDR_BASE + ADDR_CTRL
#define CHACHA_ADDR_STATUS CHACHA_ADDR_BASE + ADDR_STATUS
-#define CHACHA_ADDR_KEYLEN 0x0a
+#define CHACHA_ADDR_KEYLEN CHACHA_ADDR_BASE + 0x0a
#define CHACHA_KEYLEN 1
-#define CHACHA_ADDR_ROUNDS 0x0b
-
-#define CHACHA_ADDR_KEY0 0x10
-#define CHACHA_ADDR_KEY1 0x11
-#define CHACHA_ADDR_KEY2 0x12
-#define CHACHA_ADDR_KEY3 0x13
-#define CHACHA_ADDR_KEY4 0x14
-#define CHACHA_ADDR_KEY5 0x15
-#define CHACHA_ADDR_KEY6 0x16
-#define CHACHA_ADDR_KEY7 0x17
-
-#define CHACHA_ADDR_IV0 0x20
-#define CHACHA_ADDR_IV1 0x21
-
-#define CHACHA_ADDR_DATA_IN0 0x40
-#define CHACHA_ADDR_DATA_IN1 0x41
-#define CHACHA_ADDR_DATA_IN2 0x42
-#define CHACHA_ADDR_DATA_IN3 0x43
-#define CHACHA_ADDR_DATA_IN4 0x44
-#define CHACHA_ADDR_DATA_IN5 0x45
-#define CHACHA_ADDR_DATA_IN6 0x46
-#define CHACHA_ADDR_DATA_IN7 0x47
-#define CHACHA_ADDR_DATA_IN8 0x48
-#define CHACHA_ADDR_DATA_IN9 0x49
-#define CHACHA_ADDR_DATA_IN10 0x4a
-#define CHACHA_ADDR_DATA_IN11 0x4b
-#define CHACHA_ADDR_DATA_IN12 0x4c
-#define CHACHA_ADDR_DATA_IN13 0x4d
-#define CHACHA_ADDR_DATA_IN14 0x4e
-#define CHACHA_ADDR_DATA_IN15 0x4f
-
-#define CHACHA_ADDR_DATA_OUT0 0x80
-#define CHACHA_ADDR_DATA_OUT1 0x81
-#define CHACHA_ADDR_DATA_OUT2 0x82
-#define CHACHA_ADDR_DATA_OUT3 0x83
-#define CHACHA_ADDR_DATA_OUT4 0x84
-#define CHACHA_ADDR_DATA_OUT5 0x85
-#define CHACHA_ADDR_DATA_OUT6 0x86
-#define CHACHA_ADDR_DATA_OUT7 0x87
-#define CHACHA_ADDR_DATA_OUT8 0x88
-#define CHACHA_ADDR_DATA_OUT9 0x89
-#define CHACHA_ADDR_DATA_OUT10 0x8a
-#define CHACHA_ADDR_DATA_OUT11 0x8b
-#define CHACHA_ADDR_DATA_OUT12 0x8c
-#define CHACHA_ADDR_DATA_OUT13 0x8d
-#define CHACHA_ADDR_DATA_OUT14 0x8e
-#define CHACHA_ADDR_DATA_OUT15 0x8f
+#define CHACHA_ADDR_ROUNDS CHACHA_ADDR_BASE + 0x0b
+
+#define CHACHA_ADDR_KEY0 CHACHA_ADDR_BASE + 0x10
+#define CHACHA_ADDR_KEY1 CHACHA_ADDR_BASE + 0x11
+#define CHACHA_ADDR_KEY2 CHACHA_ADDR_BASE + 0x12
+#define CHACHA_ADDR_KEY3 CHACHA_ADDR_BASE + 0x13
+#define CHACHA_ADDR_KEY4 CHACHA_ADDR_BASE + 0x14
+#define CHACHA_ADDR_KEY5 CHACHA_ADDR_BASE + 0x15
+#define CHACHA_ADDR_KEY6 CHACHA_ADDR_BASE + 0x16
+#define CHACHA_ADDR_KEY7 CHACHA_ADDR_BASE + 0x17
+
+#define CHACHA_ADDR_IV0 CHACHA_ADDR_BASE + 0x20
+#define CHACHA_ADDR_IV1 CHACHA_ADDR_BASE + 0x21
+
+#define CHACHA_ADDR_DATA_IN0 CHACHA_ADDR_BASE + 0x40
+#define CHACHA_ADDR_DATA_IN1 CHACHA_ADDR_BASE + 0x41
+#define CHACHA_ADDR_DATA_IN2 CHACHA_ADDR_BASE + 0x42
+#define CHACHA_ADDR_DATA_IN3 CHACHA_ADDR_BASE + 0x43
+#define CHACHA_ADDR_DATA_IN4 CHACHA_ADDR_BASE + 0x44
+#define CHACHA_ADDR_DATA_IN5 CHACHA_ADDR_BASE + 0x45
+#define CHACHA_ADDR_DATA_IN6 CHACHA_ADDR_BASE + 0x46
+#define CHACHA_ADDR_DATA_IN7 CHACHA_ADDR_BASE + 0x47
+#define CHACHA_ADDR_DATA_IN8 CHACHA_ADDR_BASE + 0x48
+#define CHACHA_ADDR_DATA_IN9 CHACHA_ADDR_BASE + 0x49
+#define CHACHA_ADDR_DATA_IN10 CHACHA_ADDR_BASE + 0x4a
+#define CHACHA_ADDR_DATA_IN11 CHACHA_ADDR_BASE + 0x4b
+#define CHACHA_ADDR_DATA_IN12 CHACHA_ADDR_BASE + 0x4c
+#define CHACHA_ADDR_DATA_IN13 CHACHA_ADDR_BASE + 0x4d
+#define CHACHA_ADDR_DATA_IN14 CHACHA_ADDR_BASE + 0x4e
+#define CHACHA_ADDR_DATA_IN15 CHACHA_ADDR_BASE + 0x4f
+
+#define CHACHA_ADDR_DATA_OUT0 CHACHA_ADDR_BASE + 0x80
+#define CHACHA_ADDR_DATA_OUT1 CHACHA_ADDR_BASE + 0x81
+#define CHACHA_ADDR_DATA_OUT2 CHACHA_ADDR_BASE + 0x82
+#define CHACHA_ADDR_DATA_OUT3 CHACHA_ADDR_BASE + 0x83
+#define CHACHA_ADDR_DATA_OUT4 CHACHA_ADDR_BASE + 0x84
+#define CHACHA_ADDR_DATA_OUT5 CHACHA_ADDR_BASE + 0x85
+#define CHACHA_ADDR_DATA_OUT6 CHACHA_ADDR_BASE + 0x86
+#define CHACHA_ADDR_DATA_OUT7 CHACHA_ADDR_BASE + 0x87
+#define CHACHA_ADDR_DATA_OUT8 CHACHA_ADDR_BASE + 0x88
+#define CHACHA_ADDR_DATA_OUT9 CHACHA_ADDR_BASE + 0x89
+#define CHACHA_ADDR_DATA_OUT10 CHACHA_ADDR_BASE + 0x8a
+#define CHACHA_ADDR_DATA_OUT11 CHACHA_ADDR_BASE + 0x8b
+#define CHACHA_ADDR_DATA_OUT12 CHACHA_ADDR_BASE + 0x8c
+#define CHACHA_ADDR_DATA_OUT13 CHACHA_ADDR_BASE + 0x8d
+#define CHACHA_ADDR_DATA_OUT14 CHACHA_ADDR_BASE + 0x8e
+#define CHACHA_ADDR_DATA_OUT15 CHACHA_ADDR_BASE + 0x8f
// current name and version values
#define CHACHA_NAME0 "chac"
@@ -389,33 +389,37 @@ in order to map it into a 16-bit address space.
// MATH segment.
// -----------------------------------------------------------------
// Modexp core.
-#define GENERAL_PREFIX 0x000
-#define MODULUS_PREFIX 0x100
-#define EXPONENT_PREFIX 0x200
-#define MESSAGE_PREFIX 0x300
-#define RESULT_PREFIX 0x400
+#define MODEXP_ADDR_BASE SEGMENT_OFFSET_MATH + (0x00 * CORE_SIZE)
+#define MODEXP_ADDR_NAME0 MODEXP_ADDR_BASE + ADDR_NAME0
+#define MODEXP_ADDR_NAME1 MODEXP_ADDR_BASE + ADDR_NAME1
+#define MODEXP_ADDR_VERSION MODEXP_ADDR_BASE + ADDR_VERSION
+#define MODEXP_ADDR_CTRL MODEXP_ADDR_BASE + ADDR_CTRL
+#define MODEXP_CTRL_INIT_BIT 1
+#define MODEXP_CTRL_NEXT_BIT 2
+#define MODEXP_ADDR_STATUS MODEXP_ADDR_BASE + ADDR_STATUS
-#define MODEXP_ADDR_BASE SEGMENT_OFFSET_MATH + (0x00 * CORE_SIZE)
-#define MODEXP_ADDR_NAME0 MODEXP_ADDR_BASE + ADDR_NAME0
-#define MODEXP_ADDR_NAME1 MODEXP_ADDR_BASE + ADDR_NAME1
-#define MODEXP_ADDR_VERSION MODEXP_ADDR_BASE + ADDR_VERSION
-#define MODEXP_ADDR_CTRL MODEXP_ADDR_BASE + ADDR_CTRL
-#define MODEXP_ADDR_STATUS MODEXP_ADDR_BASE + ADDR_STATUS
+#define MODEXP_ADDR_DELAY MODEXP_ADDR_BASE + 0x13
+#define MODEXP_STATUS_READY 1
-#define MODEXP_ADDR_DELAY MODEXP_ADDR_BASE + 0x13
-#define MODEXP_STATUS_READY 1
+#define MODEXP_MODULUS_LENGTH MODEXP_ADDR_BASE + 0x20
+#define MODEXP_EXPONENT_LENGTH MODEXP_ADDR_BASE + 0x21
+#define MODEXP_LENGTH MODEXP_ADDR_BASE + 0x22
-#define MODEXP_MODULUS_LENGTH MODEXP_ADDR_BASE + 0x20
-#define MODEXP_EXPONENT_LENGTH MODEXP_ADDR_BASE + 0x21
+#define MODEXP_MODULUS_PTR_RST MODEXP_ADDR_BASE + 0x30
+#define MODEXP_MODULUS_DATA MODEXP_ADDR_BASE + 0x31
-// Most cores need fewer than 256 registers, but Modexp needs many more.
-//#define NEXT_MATH_ADDR_BASE SEGMENT_OFFSET_MATH + (0x05 * CORE_SIZE)
+#define MODEXP_EXPONENT_PTR_RST MODEXP_ADDR_BASE + 0x40
+#define MODEXP_EXPONENT_DATA MODEXP_ADDR_BASE + 0x41
-// current name and version values
-#define MODEXP_NAME0 "mode"
-#define MODEXP_NAME1 "xp "
-#define MODEXP_VERSION "0.50"
+#define MODEXP_MESSAGE_PTR_RST MODEXP_ADDR_BASE + 0x50
+#define MODEXP_MESSAGE_DATA MODEXP_ADDR_BASE + 0x51
+
+#define MODEXP_RESULT_PTR_RST MODEXP_ADDR_BASE + 0x60
+#define MODEXP_RESULT_DATA MODEXP_ADDR_BASE + 0x61
+#define MODEXP_NAME0 "mode"
+#define MODEXP_NAME1 "xp "
+#define MODEXP_VERSION "0.51"
//------------------------------------------------------------------
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