[Cryptech-Commits] [core/math/modexp] 03/03: Fixed errors in block memories.
git at cryptech.is
git at cryptech.is
Tue Jun 30 14:16:16 UTC 2015
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joachim at secworks.se pushed a commit to branch debug_bigoperands
in repository core/math/modexp.
commit 06fa4cc16f62f156143949328da7f6ab578cb365
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Tue Jun 30 16:15:30 2015 +0200
Fixed errors in block memories.
---
src/rtl/blockmem1r1w.v | 22 +++++++++++++---------
src/rtl/blockmem2r1w.v | 25 +++++++++++++------------
src/rtl/blockmem2r1wptr.v | 44 +++++++++++++++++++++++++-------------------
src/rtl/blockmem2rptr1w.v | 41 +++++++++++++++++++++++------------------
4 files changed, 74 insertions(+), 58 deletions(-)
diff --git a/src/rtl/blockmem1r1w.v b/src/rtl/blockmem1r1w.v
index 1d84369..6856e0a 100644
--- a/src/rtl/blockmem1r1w.v
+++ b/src/rtl/blockmem1r1w.v
@@ -7,6 +7,9 @@
//
// The memory is used in the modexp core.
//
+// paremeter OPW is operand word width in bits.
+// parameter ADW is address width in bits.
+//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
@@ -39,19 +42,20 @@
//
//======================================================================
-module blockmem1r1w(
- input wire clk,
+module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
- input wire [07 : 0] read_addr,
- output wire [31 : 0] read_data,
+ input wire [(ADW - 1) : 0] read_addr,
+ output wire [(OPW - 1) : 0] read_data,
- input wire wr,
- input wire [07 : 0] write_addr,
- input wire [31 : 0] write_data
+ input wire wr,
+ input wire [(ADW - 1) : 0] write_addr,
+ input wire [(OPW - 1) : 0] write_data
);
- reg [31 : 0] mem [0 : 255];
- reg [31 : 0] tmp_read_data;
+ reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
+ reg [(OPW - 1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
diff --git a/src/rtl/blockmem2r1w.v b/src/rtl/blockmem2r1w.v
index 252764f..aa44101 100644
--- a/src/rtl/blockmem2r1w.v
+++ b/src/rtl/blockmem2r1w.v
@@ -39,23 +39,24 @@
//
//======================================================================
-module blockmem2r1w(
- input wire clk,
+module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
- input wire [07 : 0] read_addr0,
- output wire [31 : 0] read_data0,
+ input wire [(ADW - 1) : 0] read_addr0,
+ output wire [(OPW - 1) : 0] read_data0,
- input wire [07 : 0] read_addr1,
- output wire [31 : 0] read_data1,
+ input wire [(ADW - 1) : 0] read_addr1,
+ output wire [(OPW - 1) : 0] read_data1,
- input wire wr,
- input wire [07 : 0] write_addr,
- input wire [31 : 0] write_data
+ input wire wr,
+ input wire [(ADW - 1) : 0] write_addr,
+ input wire [(OPW - 1) : 0] write_data
);
- reg [31 : 0] mem [0 : 255];
- reg [31 : 0] tmp_read_data0;
- reg [31 : 0] tmp_read_data1;
+ reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
+ reg [(OPW - 1) : 0] tmp_read_data0;
+ reg [(OPW - 1) : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
diff --git a/src/rtl/blockmem2r1wptr.v b/src/rtl/blockmem2r1wptr.v
index 41efc85..2435cfd 100644
--- a/src/rtl/blockmem2r1wptr.v
+++ b/src/rtl/blockmem2r1wptr.v
@@ -8,6 +8,12 @@
// when the cs signal is set. The pointer is reset to zero when
// the rst signal is asserted.
//
+//
+// NOTE: This memory needs to be rebuilt if interface 0 is changed
+// to use bigger operand widths and fewer words than interface 1.
+// This adaption is NOT automatic.
+//
+//
// The memory is used in the modexp core.
//
//
@@ -42,32 +48,32 @@
//
//======================================================================
-module blockmem2r1wptr(
- input wire clk,
- input wire reset_n,
-
- input wire [07 : 0] read_addr0,
- output wire [31 : 0] read_data0,
+module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
+ input wire reset_n,
- output wire [31 : 0] read_data1,
+ input wire [(ADW - 1) : 0] read_addr0,
+ output wire [(OPW - 1) : 0] read_data0,
- input wire rst,
- input wire cs,
- input wire wr,
- input wire [31 : 0] write_data
+ output wire [31 : 0] read_data1,
+ input wire rst,
+ input wire cs,
+ input wire wr,
+ input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
- reg [31 : 0] mem [0 : 255];
- reg [31 : 0] tmp_read_data0;
- reg [31 : 0] tmp_read_data1;
+ reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
+ reg [(OPW - 1) : 0] tmp_read_data0;
+ reg [31 : 0] tmp_read_data1;
- reg [7 : 0] ptr_reg;
- reg [7 : 0] ptr_new;
- reg ptr_we;
+ reg [7 : 0] ptr_reg;
+ reg [7 : 0] ptr_new;
+ reg ptr_we;
//----------------------------------------------------------------
@@ -94,10 +100,10 @@ module blockmem2r1wptr(
//----------------------------------------------------------------
- // reg_update
+ // ptr_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
- begin : reg_mem_update
+ begin : ptr_update
if (!reset_n)
ptr_reg <= 8'h00;
diff --git a/src/rtl/blockmem2rptr1w.v b/src/rtl/blockmem2rptr1w.v
index 4eb529e..a1d7448 100644
--- a/src/rtl/blockmem2rptr1w.v
+++ b/src/rtl/blockmem2rptr1w.v
@@ -9,6 +9,11 @@
// The memory is used in the modexp core.
//
//
+// NOTE: This memory needs to be rebuilt if interface 0 is changed
+// to use bigger operand widths and fewer words than interface 1.
+// This adaption is NOT automatic.
+//
+//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
@@ -40,33 +45,33 @@
//
//======================================================================
-module blockmem2rptr1w(
- input wire clk,
- input wire reset_n,
-
- input wire [07 : 0] read_addr0,
- output wire [31 : 0] read_data0,
+module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
+ (
+ input wire clk,
+ input wire reset_n,
- output wire [31 : 0] read_data1,
+ input wire [(ADW - 1) : 0] read_addr0,
+ output wire [(OPW - 1) : 0] read_data0,
- input wire rst,
- input wire cs,
- input wire wr,
- input wire [07 : 0] write_addr,
- input wire [31 : 0] write_data
+ output wire [31 : 0] read_data1,
+ input wire rst,
+ input wire cs,
+ input wire wr,
+ input wire [07 : 0] write_addr,
+ input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
- reg [31 : 0] mem [0 : 255];
- reg [31 : 0] tmp_read_data0;
- reg [31 : 0] tmp_read_data1;
+ reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
+ reg [(OPW - 1) : 0] tmp_read_data0;
+ reg [31 : 0] tmp_read_data1;
- reg [7 : 0] ptr_reg;
- reg [7 : 0] ptr_new;
- reg ptr_we;
+ reg [7 : 0] ptr_reg;
+ reg [7 : 0] ptr_new;
+ reg ptr_we;
//----------------------------------------------------------------
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