[Cryptech-Commits] [core/math/modexp] branch master updated (22c547c -> 0b94757)

[git at cryptech.is]

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joachim at secworks.se pushed a change to branch master
in repository core/math/modexp.

      from  22c547c   Adding the encipher/verify test case with 1024 bit RSA key by Rob.
      adds  dd795a5   Added cycle counter to the montprod testbench to measure the execution time.
      adds  fb6d1cd   More cleanup. Adding a lot of compile flags to be able to silence the testbench.
      adds  19032d1   Fixed baseline.
      adds  62b6700   Cleanup and fixing name in preparation for cycle crunch.
      adds  1ba71b2   (1) Fixing up write address register fo s mem. (2) Cleanup of loop counter.
      adds  f4fc164   Fixed prev reg:
      adds  687521d   Fixed the carry registers.
      adds  5775903   cleanup of s mem write control.
      adds  3e96b4a   Fixed non trivial yet fairly short testcases.
      adds  6ef8730   Collapsed done. Removes one cycle from each montprod.
      adds  aa58db8   Collapsing cycles for loop counter. Updating testbench to match removed cycles.
      adds  4f7b066   Fixed final big testcase to match python model.
      adds  e33ebb8   Merge of s_mux and s_write to allow cycle collapsing.
      adds  c6555a1   Fixed order of states.
      adds  a894f3a   (1) Cleaned up bit select for operand b and a. (2) Fixed name of loop counter. (3) Reordered processes to main datapath first.
      adds  46e2c53   (1) Collapsed the sm and sa adder states. Thisimoproves performance for modexp with 3%. (2) Updated montprod testbench to not use the now removed states. (3) Minor code cleanup to make it easier to work with for further improvements.
      adds  a5076bb   Update after linting after cycle collapsing.
      adds  35c08fc   Combined case statements to make it easier to follow the sequences.
      adds  c0448c8   Restored version of montprod to a version that actually works.
      adds  98e5f8c   Correct update after linting.
      adds  90337c6   Moved s logic mux control to control fsm.
      adds  1e676b4   Adding iteration flag to be used to remove zero fill of s_mem.
      adds  10d0d1e   Adding mux to allow integrating s_mem init with main adder loop.
      adds  bba9af3   Adding write control of s_mem for first iteration and adding a new stage in priority mux.
      adds  244a915   Cleanup of prodcalc.
      adds  747377f   Removing state that has been collapsed.
      adds  99f2650   Removing stale states in FSM.
      adds  c74066a   Killed off debug in RTL since we now whow info from TB.
      adds  c54b20e   Consolidated address settings, removed stale s logic mux control, removed extra lsw set.
      adds  295a9bd   Changing module interface and internal defines to use symbolic widths for operand data size and addresses. We need to update counters too.
      adds  a66de21   Adding a minor comment in the header to exmplain what the module parameters means.
      adds  5a0a6f8   Changed blockmem1r1w used in montprod to generic data and address widths. Updated instantiation to use generics.
      adds  c8c13f7   Made the adder and shifters words size generic. Updated the montprod and residue to use the generic adder and shifters.
      adds  d2a9055   Updated residue module to use generic operand size.
      adds  906b9f1   Adding module parameters for generic operand size to modexp_core and top level localparams with explanation in modexp.v to control the core instantiation.
      adds  e509e5d   montprod now supports generic operand size.
      adds  0fa3d49   Updated the 2r1w block memory to be operand size generic. Minor fix in 1r1w block memory.
      adds  435b905   Updated all modules below modexp_core has been updated to have generic operand size. Updated module integrations in modexp_core to set the operand width and address width.
      adds  feeb054   Changed name of files to reflect that the adder and the shifters are now not specifically working on 32-bit operands. HEADSUP: This breaks builds that use the old file names.
      adds  708b71f   Fixed incorrect compile time expression for sizing the memory.
      adds  6a5d579   (1) Untangled the word index address generator from the product logic. (2) Updated the montprod TB to match changed FSM states in montprod.
      adds  5c3a5cc   Corrected suffixes and cleaned up product address generation.
      adds  faa8aff   Reorganized address generation and bit index generation.
      adds  e6af58c   Small improvement in report of test result.
      adds  d5115d8   Fused the s_mem init loop into the adder loop.
      adds  6e47b80   Removed stale mux state.
      adds  cb7251b   Removed stale switch since we now do s_mem init integrated with calculation.
      adds  fe04c61   Minor nits.
      adds  97976d1   Added another state for setting s_mem_read_addr to allow shortcutting one cycle in each loop.
      adds  9d8ab27   Added a support wrapper used to test implementations of montprod with bigger operand sizes.
      adds  fb603c3   Update of montprod after test implementation with different operand sizes.
      adds  2f019d3   Removed obsolete register. Fixed name of trace signals.
      adds  79fd97b   Added test register for cycle trace. Moved index counter update under if-else to remove spurious s_mem read.
      adds  8e73cbf   Removed extra digit in test case KAT that had creeped in.
      adds  5b00f7c   Changed modexp core to use explicit exponent length to allow removal of padding of exponent and improving performance. Updated testbenches to match the changed lengths inside the device under test.
      adds  cef6c5b   Added test case with small exponent and modulus, message that requires padding to work correctly.
      adds  97de1e0   Adding hold register and bit combine to create final s_mem data with fused add and div.
      adds  0b94757   Adding note about experimental fused shift functionality in the adder stage.

No new revisions were added by this update.

Summary of changes:
 src/rtl/{adder32.v => adder.v}     |  42 +-
 src/rtl/blockmem1r1w.v             |  22 +-
 src/rtl/blockmem2r1w.v             |  25 +-
 src/rtl/blockmem2r1wptr.v          |  44 ++-
 src/rtl/blockmem2rptr1w.v          |  41 +-
 src/rtl/modexp.v                   |  77 ++--
 src/rtl/modexp_core.v              | 256 ++++++------
 src/rtl/montprod.v                 | 777 +++++++++++++++++++------------------
 src/rtl/residue.v                  | 402 ++++++++++---------
 src/rtl/{shl32.v => shl.v}         |  31 +-
 src/rtl/{shr32.v => shr.v}         |  25 +-
 src/support/rtl/montprod_wrapper.v | 153 ++++++++
 src/tb/tb_modexp.v                 | 199 ++++++++--
 src/tb/tb_modexp_autogenerated.v   |   4 +-
 src/tb/tb_montprod.v               | 757 ++++++++++++++++++++----------------
 toolruns/Makefile                  |   2 +-
 16 files changed, 1653 insertions(+), 1204 deletions(-)
 rename src/rtl/{adder32.v => adder.v} (65%)
 rename src/rtl/{shl32.v => shl.v} (77%)
 rename src/rtl/{shr32.v => shr.v} (79%)
 create mode 100644 src/support/rtl/montprod_wrapper.v